diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 61 | ||||
| -rw-r--r-- | include/opcode/cgen.h | 15 | ||||
| -rw-r--r-- | include/opcode/d30v.h | 84 | ||||
| -rw-r--r-- | include/opcode/i370.h | 265 | ||||
| -rw-r--r-- | include/opcode/i386.h | 150 | ||||
| -rw-r--r-- | include/opcode/mips.h | 13 |
6 files changed, 108 insertions, 480 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 7452c2bea..2be7ead39 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,64 +1,3 @@ -2000-03-27 Nick Clifton <nickc@cygnus.com> - - * d30v.h (SHORT_A1): Fix value. - (SHORT_AR): Renumber so that it is at the end of the list of short - instructions, not the end of the list of long instructions. - -2000-03-26 Alan Modra <alan@linuxcare.com> - - * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the - problem isn't really specific to Unixware. - (OLDGCC_COMPAT): Define. - (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with - destination %st(0). - Fix lots of comments. - -2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d30v.h: - (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. - (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. - (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. - (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. - (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. - (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. - (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. - -2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (fild, fistp): Change intel d_Suf form to fildd and - fistpd without suffix. - -2000-02-24 Nick Clifton <nickc@cygnus.com> - - * cgen.h (cgen_cpu_desc): Rename field 'flags' to - 'signed_overflow_ok_p'. - Delete prototypes for cgen_set_flags() and cgen_get_flags(). - -2000-02-24 Andrew Haley <aph@cygnus.com> - - * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. - (CGEN_CPU_TABLE): flags: new field. - Add prototypes for new functions. - -2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add some more UNIXWARE_COMPAT comments. - -2000-02-23 Linas Vepstas <linas@linas.org> - - * i370.h: New file. - -2000-02-22 Andrew Haley <aph@cygnus.com> - - * mips.h: (OPCODE_IS_MEMBER): Add comment. - -1999-12-30 Andrew Haley <aph@cygnus.com> - - * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines - whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit - insns. - 2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Qualify intel mode far call and jmp with x_Suf. diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 0cff7c826..2a5fd0da8 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -1281,10 +1281,6 @@ typedef struct cgen_cpu_desc /* Disassembler instruction hash table. */ CGEN_INSN_LIST **dis_hash_table; CGEN_INSN_LIST *dis_hash_table_entries; - - /* This field could be turned into a bitfield if room for other flags is needed. */ - unsigned int signed_overflow_ok_p; - } CGEN_CPU_TABLE; /* wip */ @@ -1387,13 +1383,4 @@ extern void cgen_put_insn_value extern const char * cgen_read_cpu_file PARAMS ((CGEN_CPU_DESC, const char * filename_)); -/* Allow signed overflow of instruction fields. */ -extern void cgen_set_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); - -/* Generate an error message if a signed field in an instruction overflows. */ -extern void cgen_clear_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); - -/* Will an error message be generated if a signed field in an instruction overflows ? */ -extern unsigned int cgen_signed_overflow_ok_p PARAMS ((CGEN_CPU_DESC)); - #endif /* CGEN_H */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h index f90b7a420..64c7c3634 100644 --- a/include/opcode/d30v.h +++ b/include/opcode/d30v.h @@ -1,5 +1,5 @@ /* d30v.h -- Header file for D30V opcode table - Copyright (C) 1997, 2000 Free Software Foundation, Inc. + Copyright 1997 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions This file is part of GDB, GAS, and the GNU binutils. @@ -85,46 +85,40 @@ struct d30v_opcode #define SHORT_A 9 #define SHORT_B1 11 #define SHORT_B2 12 -#define SHORT_B2r 13 -#define SHORT_B3 14 -#define SHORT_B3r 16 -#define SHORT_B3b 18 -#define SHORT_B3br 20 -#define SHORT_D1r 22 -#define SHORT_D2 24 -#define SHORT_D2r 26 -#define SHORT_D2Br 28 -#define SHORT_U 30 /* unary SHORT_A. ABS for example */ -#define SHORT_F 31 /* SHORT_A with flag registers */ -#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ -#define SHORT_T 35 /* for trap instruction */ -#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ -#define SHORT_CMP 38 /* special form for CMPcc */ -#define SHORT_CMPU 40 /* special form for CMPUcc */ -#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ -#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ -#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ -#define SHORT_MODINC 48 -#define SHORT_MODDEC 49 -#define SHORT_C1 50 -#define SHORT_C2 51 -#define SHORT_UF 52 -#define SHORT_A2 53 -#define SHORT_NONE 55 /* no operands */ -#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ -#define LONG 57 -#define LONG_U 58 /* unary LONG */ -#define LONG_Ur 59 /* LONG pc-relative */ -#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ -#define LONG_M 61 /* Memory long for ldb, stb */ -#define LONG_M2 62 /* Memory long for ld2w, st2w */ -#define LONG_2 63 /* LONG with 2 operands; jmptnz */ -#define LONG_2r 64 /* LONG with 2 operands; bratnz */ -#define LONG_2b 65 /* LONG_2 with modifier of 3 */ -#define LONG_2br 66 /* LONG_2r with modifier of 3 */ -#define LONG_D 67 /* for DJMPI */ -#define LONG_Dr 68 /* for DBRAI */ -#define LONG_Dbr 69 /* for repeati */ +#define SHORT_B3 13 +#define SHORT_B3b 15 +#define SHORT_D1 17 +#define SHORT_D2 19 +#define SHORT_D2B 21 +#define SHORT_U 23 /* unary SHORT_A. ABS for example */ +#define SHORT_F 25 /* SHORT_A with flag registers */ +#define SHORT_AF 27 /* SHORT_A with only the first register a flag register */ +#define SHORT_T 29 /* for trap instruction */ +#define SHORT_A5 30 /* SHORT_A with a 5-bit immediate instead of 6 */ +#define SHORT_CMP 32 /* special form for CMPcc */ +#define SHORT_CMPU 34 /* special form for CMPUcc */ +#define SHORT_A1 36 /* special form of SHORT_A for MACa opcodes where a=1 */ +#define SHORT_AA 38 /* SHORT_A with the first register an accumulator */ +#define SHORT_RA 40 /* SHORT_A with the second register an accumulator */ +#define SHORT_MODINC 42 +#define SHORT_MODDEC 43 +#define SHORT_C1 44 +#define SHORT_C2 45 +#define SHORT_UF 46 +#define SHORT_A2 47 +#define SHORT_A5S 49 +#define SHORT_NONE 51 /* no operands */ +#define LONG 52 +#define LONG_U 53 /* unary LONG */ +#define LONG_AF 54 /* LONG with the first register a flag register */ +#define LONG_CMP 55 /* special form for CMPcc and CMPUcc */ +#define LONG_M 56 /* Memory long for ldb, stb */ +#define LONG_M2 57 /* Memory long for ld2w, st2w */ +#define LONG_2 58 /* LONG with 2 operands; bratnz */ +#define LONG_2b 59 /* LONG_2 with modifier of 3 */ +#define LONG_D 60 /* for DBRAI*/ +#define LONG_Db 61 /* for repeati*/ +#define SHORT_AR 62 /* like SHORT_AA but only accept register as third parameter */ /* the execution unit(s) used */ int unit; @@ -153,9 +147,7 @@ struct d30v_opcode #define FLAG_JMP (1L<<13) /* instruction is a branch */ #define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ #define FLAG_MEM (1L<<15) /* reads/writes memory */ -#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation - New meaning: operation cannot be - combined in parallel with ADD/SUBppp. */ +#define FLAG_2WORD (1L<<16) /* 2 word/4 byte operation */ #define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ #define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ #define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ @@ -255,10 +247,6 @@ extern const struct d30v_operand d30v_operand_table[]; /* let the optimizer know that two registers are affected */ #define OPERAND_2REG (0x10000) -/* This operand is pc-relative. Note that repeati can have two immediate - operands, one of which is pcrel, the other (the IMM6U one) is not. */ -#define OPERAND_PCREL (0x20000) - /* The format table is an array of struct d30v_format. */ struct d30v_format { diff --git a/include/opcode/i370.h b/include/opcode/i370.h deleted file mode 100644 index f2049e741..000000000 --- a/include/opcode/i370.h +++ /dev/null @@ -1,265 +0,0 @@ -/* i370.h -- Header file for S/390 opcode table - Copyright 1994, 95, 98, 99, 2000 Free Software Foundation, Inc. - PowerPC version written by Ian Lance Taylor, Cygnus Support - Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef I370_H -#define I370_H - -/* The opcode table is an array of struct i370_opcode. */ -typedef union -{ - unsigned int i[2]; - unsigned short s[4]; - unsigned char b[8]; -} i370_insn_t; - -struct i370_opcode -{ - /* The opcode name. */ - const char *name; - - /* the length of the instruction */ - char len; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - i370_insn_t opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - i370_insn_t mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - unsigned long flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct i370_opcode i370_opcodes[]; -extern const int i370_num_opcodes; - -/* Values defined for the flags field of a struct i370_opcode. */ - -/* Opcode is defined for the original 360 architecture. */ -#define I370_OPCODE_360 (0x01) - -/* Opcode is defined for the 370 architecture. */ -#define I370_OPCODE_370 (0x02) - -/* Opcode is defined for the 370-XA architecture. */ -#define I370_OPCODE_370_XA (0x04) - -/* Opcode is defined for the ESA/370 architecture. */ -#define I370_OPCODE_ESA370 (0x08) - -/* Opcode is defined for the ESA/390 architecture. */ -#define I370_OPCODE_ESA390 (0x10) - -/* Opcode is defined for the ESA/390 w/ BFP facility. */ -#define I370_OPCODE_ESA390_BF (0x20) - -/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ -#define I370_OPCODE_ESA390_BS (0x40) - -/* Opcode is defined for the ESA/390 w/ checksum facility. */ -#define I370_OPCODE_ESA390_CK (0x80) - -/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ -#define I370_OPCODE_ESA390_CM (0x100) - -/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ -#define I370_OPCODE_ESA390_FX (0x200) - -/* Opcode is defined for the ESA/390 w/ HFP facility. */ -#define I370_OPCODE_ESA390_HX (0x400) - -/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ -#define I370_OPCODE_ESA390_IR (0x800) - -/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ -#define I370_OPCODE_ESA390_MI (0x1000) - -/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ -#define I370_OPCODE_ESA390_PC (0x2000) - -/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ -#define I370_OPCODE_ESA390_PL (0x4000) - -/* Opcode is defined for the ESA/390 w/ square-root facility. */ -#define I370_OPCODE_ESA390_QR (0x8000) - -/* Opcode is defined for the ESA/390 w/ resume-program facility. */ -#define I370_OPCODE_ESA390_RP (0x10000) - -/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ -#define I370_OPCODE_ESA390_SA (0x20000) - -/* Opcode is defined for the ESA/390 w/ subspace group facility. */ -#define I370_OPCODE_ESA390_SG (0x40000) - -/* Opcode is defined for the ESA/390 w/ string facility. */ -#define I370_OPCODE_ESA390_SR (0x80000) - -/* Opcode is defined for the ESA/390 w/ trap facility. */ -#define I370_OPCODE_ESA390_TR (0x100000) - -#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) - - -/* The operands table is an array of struct i370_operand. */ - -struct i370_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - i370_insn_t (*insert) PARAMS ((i370_insn_t instruction, long op, - const char **errmsg)); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & I370_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((i370_insn_t instruction, int *invalid)); - - /* One bit syntax flags. */ - unsigned long flags; - - /* name -- handy for debugging, otherwise pointless */ - char * name; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the i370_opcodes table. */ - -extern const struct i370_operand i370_operands[]; - -/* Values defined for the flags field of a struct i370_operand. */ - -/* This operand should be wrapped in parentheses rather than - separated from the previous by a comma. This is used for S, RS and - SS form instructions which want their operands to look like - reg,displacement(basereg) */ -#define I370_OPERAND_SBASE (0x01) - -/* This operand is a base register. It may or may not appear next - to an index register, i.e. either of the two forms - reg,displacement(basereg) - reg,displacement(index,basereg) */ -#define I370_OPERAND_BASE (0x02) - -/* This pair of operands should be wrapped in parentheses rather than - separated from the last by a comma. This is used for the RX form - instructions which want their operands to look like - reg,displacement(index,basereg) */ -#define I370_OPERAND_INDEX (0x04) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define I370_OPERAND_GPR (0x08) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define I370_OPERAND_FPR (0x10) - -/* This operand is a displacement. */ -#define I370_OPERAND_RELATIVE (0x20) - -/* This operand is a length, such as that in SS form instructions. */ -#define I370_OPERAND_LENGTH (0x40) - -/* This operand is optional, and is zero if omitted. This is used for - the optional B2 field in the shift-left, shift-right instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define I370_OPERAND_OPTIONAL (0x80) - - -/* Define some misc macros. We keep them with the operands table - for simplicity. The macro table is an array of struct i370_macro. */ - -struct i370_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct i370_opcode flags field. */ - unsigned long flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct i370_macro i370_macros[]; -extern const int i370_num_macros; - - -#endif /* I370_H */ diff --git a/include/opcode/i386.h b/include/opcode/i386.h index d399f4eb2..7bddbed4e 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -17,35 +17,28 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived - ix86 Unix assemblers, generate floating point instructions with - reversed source and destination registers in certain cases. - Unfortunately, gcc and possibly many other programs use this - reversed syntax, so we're stuck with it. +/* The UnixWare assembler, and probably other AT&T derived ix86 Unix + assemblers, generate floating point instructions with reversed + source and destination registers in certain cases. Unfortunately, + gcc and possibly many other programs use this reversed syntax, so + we're stuck with it. - eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but - `fsub %st,%st(3)' results in st(3) = st - st(3), rather than - the expected st(3) = st(3) - st + eg. `fsub %st(3),%st' results in st <- st - st(3) as expected, but + `fsub %st,%st(3)' results in st(3) <- st - st(3), rather than + the expected st(3) <- st(3) - st ! This happens with all the non-commutative arithmetic floating point operations with two register operands, where the source register is - %st, and destination register is %st(i). See FloatDR below. + %st, and destination register is %st(i). Look for FloatDR below. */ - The affected opcode map is dceX, dcfX, deeX, defX. */ - -#ifndef SYSV386_COMPAT +#ifndef UNIXWARE_COMPAT /* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes at your peril. gcc generates SystemV/386 + non-broken opcodes at your peril. gcc generates UnixWare compatible instructions. */ -#define SYSV386_COMPAT 1 -#endif -#ifndef OLDGCC_COMPAT -/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could - generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands - reversed. */ -#define OLDGCC_COMPAT SYSV386_COMPAT +#define UNIXWARE_COMPAT 1 #endif + static const template i386_optab[] = { #define X None @@ -70,16 +63,13 @@ static const template i386_optab[] = { #define sl_FP (sl_Suf|IgnoreSize) #define sld_FP (sld_Suf|IgnoreSize) #define sldx_FP (sldx_Suf|IgnoreSize) -#if SYSV386_COMPAT -/* Someone forgot that the FloatR bit reverses the operation when not - equal to the FloatD bit. ie. Changing only FloatD results in the - destination being swapped *and* the direction being reversed. */ +#if UNIXWARE_COMPAT #define FloatDR FloatD #else #define FloatDR (FloatD|FloatR) #endif -/* Move instructions. */ +/* move instructions */ #define MOV_AX_DISP32 0xa0 { "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, { "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } }, @@ -92,12 +82,12 @@ static const template i386_optab[] = { the implementation defined value is zero). */ { "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, { "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } }, -/* Move to/from control debug registers. */ +/* move to/from control debug registers */ { "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, { "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, { "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, -/* Move with sign extend. */ +/* move with sign extend */ /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid conflict with the "movs" string move instruction. */ {"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, @@ -107,38 +97,40 @@ static const template i386_optab[] = { {"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, {"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -/* Move with zero extend. */ +/* move with zero extend */ {"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, {"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* Intel Syntax */ {"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, {"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -/* Push instructions. */ +/* push instructions */ {"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, {"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, {"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, {"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, {"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, {"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +/* push all */ {"pusha", 0, 0x60, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, -/* Pop instructions. */ +/* pop instructions */ {"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, {"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, #define POP_SEG_SHORT 0x07 {"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, {"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +/* pop all */ {"popa", 0, 0x61, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, -/* Exchange instructions. - xchg commutes: we allow both operand orders. */ +/* xchg exchange instructions + xchg commutes: we allow both operand orders */ {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, -/* In/out from ports. */ +/* in/out from ports */ {"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } }, {"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, {"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } }, @@ -148,17 +140,17 @@ static const template i386_optab[] = { {"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } }, {"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, -/* Load effective address. */ +/* load effective address */ {"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } }, -/* Load segment registers from memory. */ +/* load segment registers from memory */ {"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, {"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -/* Flags register instructions. */ +/* flags register instructions */ {"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} }, {"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} }, {"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} }, @@ -172,7 +164,7 @@ static const template i386_optab[] = { {"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} }, {"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} }, -/* Arithmetic. */ +/* arithmetic */ {"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, {"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, {"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} }, @@ -219,7 +211,7 @@ static const template i386_optab[] = { {"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} }, {"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, -/* iclr with 1 operand is really xor with 2 operands. */ +/* iclr with 1 operand is really xor with 2 operands. */ {"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, {"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, @@ -239,13 +231,13 @@ static const template i386_optab[] = { {"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} }, {"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} }, -/* Conversion insns. */ -/* Intel naming */ +/* conversion insns */ +/* conversion: intel naming */ {"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, {"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, {"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, {"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, -/* AT&T naming */ +/* att naming */ {"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, {"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, {"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, @@ -318,7 +310,7 @@ static const template i386_optab[] = { {"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, {"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -/* Control transfer instructions. */ +/* control transfer instructions */ {"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, {"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ @@ -345,7 +337,7 @@ static const template i386_optab[] = { {"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, {"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} }, -/* Conditional jumps. */ +/* conditional jumps */ {"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} }, {"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} }, {"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, @@ -391,7 +383,7 @@ static const template i386_optab[] = { {"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, {"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, -/* Set byte on flag instructions. */ +/* set byte on flag instructions */ {"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, {"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, {"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, @@ -423,7 +415,7 @@ static const template i386_optab[] = { {"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, {"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -/* String manipulation. */ +/* string manipulation */ {"cmps", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, {"cmps", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, {"scmp", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, @@ -457,7 +449,7 @@ static const template i386_optab[] = { {"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} }, {"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} }, -/* Bit manipulation. */ +/* bit manipulation */ {"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, @@ -469,25 +461,25 @@ static const template i386_optab[] = { {"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, {"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -/* Interrupts & op. sys insns. */ +/* interrupts & op. sys insns */ /* See gas/config/tc-i386.c for conversion of 'int $3' into the special - int 3 insn. */ + int 3 insn. */ #define INT_OPCODE 0xcd #define INT3_OPCODE 0xcc {"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} }, {"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} }, {"into", 0, 0xce, X, NoSuf, { 0, 0, 0} }, {"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} }, -/* i386sl, i486sl, later 486, and Pentium. */ +/* i386sl, i486sl, later 486, and Pentium */ {"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} }, {"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} }, {"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} }, -/* nop is actually 'xchgl %eax, %eax'. */ +/* nop is actually 'xchgl %eax, %eax' */ {"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} }, -/* Protection control. */ +/* protection control */ {"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, {"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} }, @@ -506,7 +498,7 @@ static const template i386_optab[] = { {"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -/* Floating point instructions. */ +/* floating point instructions */ /* load */ {"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */ @@ -516,7 +508,7 @@ static const template i386_optab[] = { {"fld", 1, 0xdb, 5, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */ {"fild", 1, 0xdf, 0, sl_Suf|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */ /* Intel Syntax */ -{"fildd", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ +{"fild", 1, 0xdf, 5, d_Suf|IgnoreSize|Modrm,{ LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ {"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ {"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ {"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */ @@ -536,7 +528,7 @@ static const template i386_optab[] = { {"fstp", 1, 0xdb, 7, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */ {"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */ /* Intel Syntax */ -{"fistpd", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ +{"fistp", 1, 0xdf, 7, d_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ {"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ {"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ {"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */ @@ -585,7 +577,7 @@ static const template i386_optab[] = { /* add */ {"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, {"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */ -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, /* alias for faddp */ #endif {"fadd", 1, 0xd8, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, @@ -599,19 +591,17 @@ static const template i386_optab[] = { /* subtract */ {"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubp */ #endif {"fsub", 1, 0xd8, 4, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT {"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif #else {"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -621,19 +611,17 @@ static const template i386_optab[] = { /* subtract reverse */ {"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubrp */ #endif {"fsubr", 1, 0xd8, 5, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT {"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif #else {"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -643,7 +631,7 @@ static const template i386_optab[] = { /* multiply */ {"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, {"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fmulp */ #endif {"fmul", 1, 0xd8, 1, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, @@ -657,19 +645,17 @@ static const template i386_optab[] = { /* divide */ {"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivp */ #endif {"fdiv", 1, 0xd8, 6, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fidiv", 1, 0xde, 6, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT {"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif #else {"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -679,19 +665,17 @@ static const template i386_optab[] = { /* divide reverse */ {"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, {"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivrp */ #endif {"fdivr", 1, 0xd8, 7, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, {"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -#if SYSV386_COMPAT +#if UNIXWARE_COMPAT {"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, {"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT {"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif #else {"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, @@ -731,7 +715,8 @@ static const template i386_optab[] = { {"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} }, {"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} }, {"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} }, -/* Short forms of fldenv, fstenv use data size prefix. */ +/* Short forms of fldenv, fstenv use data size prefix. + FIXME: Are these the right suffixes? */ {"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, {"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, {"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, @@ -746,8 +731,9 @@ static const template i386_optab[] = { #define FWAIT_OPCODE 0x9b {"fwait", 0, 0x9b, X, FP, { 0, 0, 0} }, -/* Opcode prefixes; we allow them as separate insns too. */ - +/* + opcode prefixes; we allow them as seperate insns too +*/ #define ADDR_PREFIX_OPCODE 0x67 {"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, {"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, @@ -781,7 +767,7 @@ static const template i386_optab[] = { {"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, {"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, -/* 486 extensions. */ +/* 486 extensions */ {"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } }, {"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, @@ -790,10 +776,10 @@ static const template i386_optab[] = { {"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} }, {"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} }, -/* 586 and late 486 extensions. */ +/* 586 and late 486 extensions */ {"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} }, -/* Pentium extensions. */ +/* Pentium extensions */ {"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} }, {"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} }, {"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} }, @@ -803,7 +789,7 @@ static const template i386_optab[] = { {"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, {"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, -/* Pentium Pro extensions. */ +/* Pentium Pro extensions */ {"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} }, {"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* official undefined instr. */ @@ -928,7 +914,7 @@ static const template i386_optab[] = { {"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -/* PIII Katmai New Instructions / SIMD instructions. */ +/* PIII Katmai New Instructions / SIMD instructions */ {"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, @@ -1017,7 +1003,7 @@ static const template i386_optab[] = { {"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -/* AMD 3DNow! instructions. */ +/* AMD 3DNow! instructions */ {"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } }, {"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } }, @@ -1075,7 +1061,7 @@ static const template i386_optab[] = { #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ -/* 386 register table. */ +/* 386 register table */ static const reg_entry i386_regtab[] = { /* make %st first as we test for it */ diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 68fe57a8a..8c93d1bd7 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -320,21 +320,14 @@ struct mips_opcode /* Toshiba R3900 instruction. */ #define INSN_3900 0x00000080 -/* 32-bit code running on a ISA3+ CPU. */ -#define INSN_GP32 0x00001000 - /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. - The gp32 arg is set when you need to force 32-bit register usage on - a machine with 64-bit registers; see the documentation under -mgp32 - in the MIPS gas docs. */ + to test, or zero if no CPU specific ISA test is desired. */ -#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \ +#define OPCODE_IS_MEMBER(insn,isa,cpu) \ ((((insn)->membership & INSN_ISA) != 0 \ - && ((insn)->membership & INSN_ISA) <= isa \ - && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ + && ((insn)->membership & INSN_ISA) <= isa) \ || (cpu == 4650 \ && ((insn)->membership & INSN_4650) != 0) \ || (cpu == 4010 \ |