This commit was manufactured by cvs2svn to create branchmultiprocess-20081120-branchpoint

'multiprocess-20081120-branch'. Sprout from master 2008-11-19 18:25:19 UTC Bob Wilson <bob.wilson@acm.org> 'include/' Cherrypick from cygnus 1999-05-03 07:29:06 UTC Richard Henderson <rth@redhat.com> '19990502 sourceware import': README config/mt-d30v config/mt-netware config/mt-ospace etc/add-log.el etc/add-log.vi etc/configbuild.ein etc/configbuild.fig etc/configbuild.jin etc/configbuild.tin etc/configdev.ein etc/configdev.fig etc/configdev.jin etc/configdev.tin include/aout/hppa.h include/coff/sym.h include/fopen-bin.h include/fopen-same.h include/opcode/tahoe.h makefile.vms Delete: libgloss/ChangeLog libgloss/Makefile.in libgloss/README libgloss/acinclude.m4 libgloss/aclocal.m4 libgloss/arm/Makefile.in libgloss/arm/_exit.c libgloss/arm/_kill.c libgloss/arm/aclocal.m4 libgloss/arm/coff-iq80310.specs libgloss/arm/coff-pid.specs libgloss/arm/coff-rdimon.specs libgloss/arm/coff-rdpmon.specs libgloss/arm/coff-redboot.ld libgloss/arm/coff-redboot.specs libgloss/arm/configure libgloss/arm/configure.in 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newlib/libc/sys/a29khif/sys/fpsymbol.h newlib/libc/sys/a29khif/sys/intrinsi.h newlib/libc/sys/a29khif/sys/macros.h newlib/libc/sys/a29khif/sys/proreg.h newlib/libc/sys/a29khif/sys/romdcl.h newlib/libc/sys/a29khif/sys/smartmac.h newlib/libc/sys/a29khif/sys/sysmac.h newlib/libc/sys/a29khif/systime.S newlib/libc/sys/a29khif/vec.S newlib/libc/sys/aclocal.m4 newlib/libc/sys/arc/Makefile.am newlib/libc/sys/arc/Makefile.in newlib/libc/sys/arc/aclocal.m4 newlib/libc/sys/arc/configure newlib/libc/sys/arc/configure.in newlib/libc/sys/arc/crt0.S newlib/libc/sys/arc/dummy.S newlib/libc/sys/arc/isatty.c newlib/libc/sys/arc/mem-layout.c newlib/libc/sys/arc/sbrk.c newlib/libc/sys/arc/sys/syscall.h newlib/libc/sys/arc/syscalls.c newlib/libc/sys/arm/Makefile.am newlib/libc/sys/arm/Makefile.in newlib/libc/sys/arm/aclocal.m4 newlib/libc/sys/arm/aeabi_atexit.c newlib/libc/sys/arm/configure newlib/libc/sys/arm/configure.in newlib/libc/sys/arm/crt0.S newlib/libc/sys/arm/libcfunc.c newlib/libc/sys/arm/swi.h newlib/libc/sys/arm/sys/fcntl.h newlib/libc/sys/arm/sys/param.h newlib/libc/sys/arm/syscalls.c newlib/libc/sys/arm/trap.S newlib/libc/sys/configure newlib/libc/sys/configure.in newlib/libc/sys/d10v/Makefile.am newlib/libc/sys/d10v/Makefile.in newlib/libc/sys/d10v/aclocal.m4 newlib/libc/sys/d10v/configure newlib/libc/sys/d10v/configure.in newlib/libc/sys/d10v/creat.c newlib/libc/sys/d10v/crt0.S newlib/libc/sys/d10v/sys/syscall.h newlib/libc/sys/d10v/syscalls.c newlib/libc/sys/d10v/trap.S newlib/libc/sys/decstation/Makefile.am newlib/libc/sys/decstation/Makefile.in newlib/libc/sys/decstation/_main.c newlib/libc/sys/decstation/aclocal.m4 newlib/libc/sys/decstation/configure newlib/libc/sys/decstation/configure.in newlib/libc/sys/decstation/sys/dirent.h newlib/libc/sys/h8300hms/Makefile.am newlib/libc/sys/h8300hms/Makefile.in newlib/libc/sys/h8300hms/_exit.S newlib/libc/sys/h8300hms/aclocal.m4 newlib/libc/sys/h8300hms/close.S newlib/libc/sys/h8300hms/configure newlib/libc/sys/h8300hms/configure.in newlib/libc/sys/h8300hms/crt0.S newlib/libc/sys/h8300hms/crt1.c newlib/libc/sys/h8300hms/fstat.S newlib/libc/sys/h8300hms/lseek.S newlib/libc/sys/h8300hms/misc.c newlib/libc/sys/h8300hms/open.S newlib/libc/sys/h8300hms/read.S newlib/libc/sys/h8300hms/sbrk.c newlib/libc/sys/h8300hms/setarch.h newlib/libc/sys/h8300hms/stat.S newlib/libc/sys/h8300hms/sys/file.h newlib/libc/sys/h8300hms/sys/syscall.h newlib/libc/sys/h8300hms/syscalls.c newlib/libc/sys/h8300hms/write.S newlib/libc/sys/h8500hms/Makefile.am newlib/libc/sys/h8500hms/Makefile.in newlib/libc/sys/h8500hms/aclocal.m4 newlib/libc/sys/h8500hms/configure newlib/libc/sys/h8500hms/configure.in newlib/libc/sys/h8500hms/crt0.c newlib/libc/sys/h8500hms/misc.c newlib/libc/sys/h8500hms/syscalls.c newlib/libc/sys/linux/Makefile.am newlib/libc/sys/linux/Makefile.in newlib/libc/sys/linux/aclocal.m4 newlib/libc/sys/linux/aio.c newlib/libc/sys/linux/aio64.c newlib/libc/sys/linux/argp/Makefile.am newlib/libc/sys/linux/argp/Makefile.in newlib/libc/sys/linux/argp/argp-ba.c newlib/libc/sys/linux/argp/argp-eexst.c newlib/libc/sys/linux/argp/argp-fmtstream.c newlib/libc/sys/linux/argp/argp-fmtstream.h newlib/libc/sys/linux/argp/argp-fs-xinl.c newlib/libc/sys/linux/argp/argp-help.c newlib/libc/sys/linux/argp/argp-namefrob.h newlib/libc/sys/linux/argp/argp-parse.c newlib/libc/sys/linux/argp/argp-pv.c newlib/libc/sys/linux/argp/argp-pvh.c newlib/libc/sys/linux/argp/argp-xinl.c newlib/libc/sys/linux/bits/initspin.h newlib/libc/sys/linux/bits/libc-lock.h newlib/libc/sys/linux/bits/pthreadtypes.h newlib/libc/sys/linux/bits/typesizes.h newlib/libc/sys/linux/bp-checks.h newlib/libc/sys/linux/brk.c newlib/libc/sys/linux/calloc.c newlib/libc/sys/linux/callocr.c newlib/libc/sys/linux/cfreer.c newlib/libc/sys/linux/cfspeed.c newlib/libc/sys/linux/clock_getres.c newlib/libc/sys/linux/clock_gettime.c newlib/libc/sys/linux/clock_settime.c newlib/libc/sys/linux/cmath/Makefile.am newlib/libc/sys/linux/cmath/Makefile.in newlib/libc/sys/linux/cmath/math_private.h newlib/libc/sys/linux/cmath/s_cacos.c newlib/libc/sys/linux/cmath/s_cacosf.c newlib/libc/sys/linux/cmath/s_cacosh.c newlib/libc/sys/linux/cmath/s_cacoshf.c newlib/libc/sys/linux/cmath/s_cacoshl.c newlib/libc/sys/linux/cmath/s_cacosl.c newlib/libc/sys/linux/cmath/s_casin.c newlib/libc/sys/linux/cmath/s_casinf.c newlib/libc/sys/linux/cmath/s_casinh.c newlib/libc/sys/linux/cmath/s_casinhf.c newlib/libc/sys/linux/cmath/s_casinhl.c newlib/libc/sys/linux/cmath/s_casinl.c newlib/libc/sys/linux/cmath/s_catan.c newlib/libc/sys/linux/cmath/s_catanf.c newlib/libc/sys/linux/cmath/s_catanh.c newlib/libc/sys/linux/cmath/s_catanhf.c newlib/libc/sys/linux/cmath/s_catanhl.c newlib/libc/sys/linux/cmath/s_catanl.c newlib/libc/sys/linux/cmath/s_cbrtl.c newlib/libc/sys/linux/cmath/s_ccos.c newlib/libc/sys/linux/cmath/s_ccosf.c newlib/libc/sys/linux/cmath/s_ccosh.c newlib/libc/sys/linux/cmath/s_ccoshf.c newlib/libc/sys/linux/cmath/s_ccoshl.c newlib/libc/sys/linux/cmath/s_ccosl.c newlib/libc/sys/linux/cmath/s_cexp.c newlib/libc/sys/linux/cmath/s_cexpf.c newlib/libc/sys/linux/cmath/s_cexpl.c newlib/libc/sys/linux/cmath/s_clog.c newlib/libc/sys/linux/cmath/s_clog10.c newlib/libc/sys/linux/cmath/s_clog10f.c newlib/libc/sys/linux/cmath/s_clog10l.c newlib/libc/sys/linux/cmath/s_clogf.c newlib/libc/sys/linux/cmath/s_clogl.c newlib/libc/sys/linux/cmath/s_cpow.c newlib/libc/sys/linux/cmath/s_cpowf.c newlib/libc/sys/linux/cmath/s_cpowl.c newlib/libc/sys/linux/cmath/s_cproj.c newlib/libc/sys/linux/cmath/s_cprojf.c newlib/libc/sys/linux/cmath/s_cprojl.c newlib/libc/sys/linux/cmath/s_csin.c newlib/libc/sys/linux/cmath/s_csinf.c newlib/libc/sys/linux/cmath/s_csinh.c newlib/libc/sys/linux/cmath/s_csinhf.c newlib/libc/sys/linux/cmath/s_csinhl.c newlib/libc/sys/linux/cmath/s_csinl.c newlib/libc/sys/linux/cmath/s_csqrt.c newlib/libc/sys/linux/cmath/s_csqrtf.c newlib/libc/sys/linux/cmath/s_csqrtl.c newlib/libc/sys/linux/cmath/s_ctan.c newlib/libc/sys/linux/cmath/s_ctanf.c newlib/libc/sys/linux/cmath/s_ctanh.c newlib/libc/sys/linux/cmath/s_ctanhf.c newlib/libc/sys/linux/cmath/s_ctanhl.c newlib/libc/sys/linux/cmath/s_ctanl.c newlib/libc/sys/linux/config.h newlib/libc/sys/linux/configure newlib/libc/sys/linux/configure.in newlib/libc/sys/linux/confstr.c newlib/libc/sys/linux/confstr.h newlib/libc/sys/linux/crt1.c newlib/libc/sys/linux/ctermid.c newlib/libc/sys/linux/dl/Makefile.am newlib/libc/sys/linux/dl/Makefile.in newlib/libc/sys/linux/dl/abi-tag.h newlib/libc/sys/linux/dl/atomicity.h newlib/libc/sys/linux/dl/dl-addr.c newlib/libc/sys/linux/dl/dl-cache.c newlib/libc/sys/linux/dl/dl-cache.h newlib/libc/sys/linux/dl/dl-close.c newlib/libc/sys/linux/dl/dl-debug.c newlib/libc/sys/linux/dl/dl-deps.c newlib/libc/sys/linux/dl/dl-dst.h newlib/libc/sys/linux/dl/dl-error.c newlib/libc/sys/linux/dl/dl-fini.c newlib/libc/sys/linux/dl/dl-init.c newlib/libc/sys/linux/dl/dl-iteratephdr.c newlib/libc/sys/linux/dl/dl-libc.c newlib/libc/sys/linux/dl/dl-librecon.h newlib/libc/sys/linux/dl/dl-load.c newlib/libc/sys/linux/dl/dl-local.h newlib/libc/sys/linux/dl/dl-lookup.c newlib/libc/sys/linux/dl/dl-lookupcfg.h newlib/libc/sys/linux/dl/dl-minimal.c newlib/libc/sys/linux/dl/dl-misc.c newlib/libc/sys/linux/dl/dl-object.c newlib/libc/sys/linux/dl/dl-open.c newlib/libc/sys/linux/dl/dl-osinfo.h newlib/libc/sys/linux/dl/dl-profile.c newlib/libc/sys/linux/dl/dl-profstub.c newlib/libc/sys/linux/dl/dl-reloc.c newlib/libc/sys/linux/dl/dl-runtime.c newlib/libc/sys/linux/dl/dl-support.c newlib/libc/sys/linux/dl/dl-sym.c newlib/libc/sys/linux/dl/dl-version.c newlib/libc/sys/linux/dl/do-lookup.h newlib/libc/sys/linux/dl/do-rel.h newlib/libc/sys/linux/dl/dynamic-link.h newlib/libc/sys/linux/dl/kernel-features.h newlib/libc/sys/linux/dl/ldsodefs.h newlib/libc/sys/linux/dl/libintl.h newlib/libc/sys/linux/dl/trusted-dirs.h newlib/libc/sys/linux/dl/unsecvars.h newlib/libc/sys/linux/fclean.c newlib/libc/sys/linux/flockfile.c newlib/libc/sys/linux/fpathconf.c newlib/libc/sys/linux/free.c newlib/libc/sys/linux/freer.c newlib/libc/sys/linux/fstab.c newlib/libc/sys/linux/fstatvfs.c newlib/libc/sys/linux/fstatvfs64.c newlib/libc/sys/linux/ftok.c newlib/libc/sys/linux/ftw.c newlib/libc/sys/linux/ftw64.c newlib/libc/sys/linux/funlockfile.c newlib/libc/sys/linux/getdate.c newlib/libc/sys/linux/getdate_err.c newlib/libc/sys/linux/gethostid.c newlib/libc/sys/linux/gethostname.c newlib/libc/sys/linux/getlogin.c newlib/libc/sys/linux/getopt.c newlib/libc/sys/linux/getopt1.c newlib/libc/sys/linux/getpwent.c newlib/libc/sys/linux/getreent.c newlib/libc/sys/linux/getrlimit64.c newlib/libc/sys/linux/getwd.c newlib/libc/sys/linux/hp-timing.h newlib/libc/sys/linux/iconv/Makefile.am newlib/libc/sys/linux/iconv/Makefile.in newlib/libc/sys/linux/iconv/categories.def newlib/libc/sys/linux/iconv/dummy-repertoire.c newlib/libc/sys/linux/iconv/gconv.c newlib/libc/sys/linux/iconv/gconv_builtin.c newlib/libc/sys/linux/iconv/gconv_builtin.h newlib/libc/sys/linux/iconv/gconv_cache.c newlib/libc/sys/linux/iconv/gconv_charset.h newlib/libc/sys/linux/iconv/gconv_close.c newlib/libc/sys/linux/iconv/gconv_conf.c newlib/libc/sys/linux/iconv/gconv_db.c newlib/libc/sys/linux/iconv/gconv_dl.c newlib/libc/sys/linux/iconv/gconv_int.h newlib/libc/sys/linux/iconv/gconv_open.c newlib/libc/sys/linux/iconv/gconv_simple.c newlib/libc/sys/linux/iconv/gconv_trans.c newlib/libc/sys/linux/iconv/hash-string.h newlib/libc/sys/linux/iconv/iconv.c newlib/libc/sys/linux/iconv/iconv.h newlib/libc/sys/linux/iconv/iconv_charmap.c newlib/libc/sys/linux/iconv/iconv_close.c newlib/libc/sys/linux/iconv/iconv_open.c newlib/libc/sys/linux/iconv/iconvconfig.h newlib/libc/sys/linux/iconv/loadinfo.h newlib/libc/sys/linux/iconv/localeinfo.h newlib/libc/sys/linux/iconv/loop.c newlib/libc/sys/linux/iconv/skeleton.c newlib/libc/sys/linux/ids.c newlib/libc/sys/linux/include/argp.h newlib/libc/sys/linux/include/arpa/ftp.h newlib/libc/sys/linux/include/arpa/inet.h newlib/libc/sys/linux/include/arpa/nameser.h newlib/libc/sys/linux/include/arpa/nameser_compat.h newlib/libc/sys/linux/include/arpa/telnet.h newlib/libc/sys/linux/include/arpa/tftp.h newlib/libc/sys/linux/include/bp-sym.h newlib/libc/sys/linux/include/cmathcalls.h newlib/libc/sys/linux/include/complex.h newlib/libc/sys/linux/include/dl-hash.h newlib/libc/sys/linux/include/dlfcn.h newlib/libc/sys/linux/include/fnmatch.h newlib/libc/sys/linux/include/gconv.h newlib/libc/sys/linux/include/getopt.h newlib/libc/sys/linux/include/glob.h newlib/libc/sys/linux/include/hesiod.h newlib/libc/sys/linux/include/iconv.h newlib/libc/sys/linux/include/ifaddrs.h newlib/libc/sys/linux/include/limits.h newlib/libc/sys/linux/include/link.h newlib/libc/sys/linux/include/ltdl.h newlib/libc/sys/linux/include/malloc.h newlib/libc/sys/linux/include/mcheck.h newlib/libc/sys/linux/include/mqueue.h newlib/libc/sys/linux/include/namespace.h newlib/libc/sys/linux/include/net/bpf.h newlib/libc/sys/linux/include/net/bpf_compat.h newlib/libc/sys/linux/include/net/bpfdesc.h newlib/libc/sys/linux/include/net/bridge.h newlib/libc/sys/linux/include/net/ethernet.h newlib/libc/sys/linux/include/net/fddi.h newlib/libc/sys/linux/include/net/if.h newlib/libc/sys/linux/include/net/if_arc.h newlib/libc/sys/linux/include/net/if_arp.h newlib/libc/sys/linux/include/net/if_dl.h newlib/libc/sys/linux/include/net/if_gif.h newlib/libc/sys/linux/include/net/if_ieee80211.h newlib/libc/sys/linux/include/net/if_llc.h newlib/libc/sys/linux/include/net/if_mib.h newlib/libc/sys/linux/include/net/if_ppp.h newlib/libc/sys/linux/include/net/if_slvar.h newlib/libc/sys/linux/include/net/if_sppp.h newlib/libc/sys/linux/include/net/if_stf.h newlib/libc/sys/linux/include/net/if_tap.h newlib/libc/sys/linux/include/net/if_tapvar.h newlib/libc/sys/linux/include/net/if_tun.h newlib/libc/sys/linux/include/net/if_tunvar.h newlib/libc/sys/linux/include/net/if_types.h newlib/libc/sys/linux/include/net/if_var.h newlib/libc/sys/linux/include/net/if_vlan_var.h newlib/libc/sys/linux/include/net/intrq.h newlib/libc/sys/linux/include/net/iso88025.h newlib/libc/sys/linux/include/net/net_osdep.h newlib/libc/sys/linux/include/net/netisr.h newlib/libc/sys/linux/include/net/pfil.h newlib/libc/sys/linux/include/net/pfkeyv2.h newlib/libc/sys/linux/include/net/ppp_comp.h newlib/libc/sys/linux/include/net/ppp_defs.h newlib/libc/sys/linux/include/net/radix.h newlib/libc/sys/linux/include/net/raw_cb.h newlib/libc/sys/linux/include/net/route.h newlib/libc/sys/linux/include/net/slcompress.h newlib/libc/sys/linux/include/net/slip.h newlib/libc/sys/linux/include/net/zlib.h newlib/libc/sys/linux/include/netconfig.h newlib/libc/sys/linux/include/netdb.h newlib/libc/sys/linux/include/netinet/icmp6.h newlib/libc/sys/linux/include/netinet/icmp_var.h newlib/libc/sys/linux/include/netinet/if_ether.h newlib/libc/sys/linux/include/netinet/igmp.h newlib/libc/sys/linux/include/netinet/igmp_var.h newlib/libc/sys/linux/include/netinet/in.h newlib/libc/sys/linux/include/netinet/in_gif.h newlib/libc/sys/linux/include/netinet/in_pcb.h newlib/libc/sys/linux/include/netinet/in_systm.h newlib/libc/sys/linux/include/netinet/in_var.h newlib/libc/sys/linux/include/netinet/ip.h newlib/libc/sys/linux/include/netinet/ip6.h newlib/libc/sys/linux/include/netinet/ip_dummynet.h newlib/libc/sys/linux/include/netinet/ip_ecn.h newlib/libc/sys/linux/include/netinet/ip_encap.h newlib/libc/sys/linux/include/netinet/ip_fw.h newlib/libc/sys/linux/include/netinet/ip_icmp.h newlib/libc/sys/linux/include/netinet/ip_mroute.h newlib/libc/sys/linux/include/netinet/ip_var.h newlib/libc/sys/linux/include/netinet/ipprotosw.h newlib/libc/sys/linux/include/netinet/tcp.h newlib/libc/sys/linux/include/netinet/tcp_debug.h newlib/libc/sys/linux/include/netinet/tcp_fsm.h newlib/libc/sys/linux/include/netinet/tcp_seq.h newlib/libc/sys/linux/include/netinet/tcp_timer.h newlib/libc/sys/linux/include/netinet/tcp_var.h newlib/libc/sys/linux/include/netinet/tcpip.h newlib/libc/sys/linux/include/netinet/udp.h newlib/libc/sys/linux/include/netinet/udp_var.h newlib/libc/sys/linux/include/netinet6/ah.h newlib/libc/sys/linux/include/netinet6/ah6.h newlib/libc/sys/linux/include/netinet6/esp.h newlib/libc/sys/linux/include/netinet6/esp6.h newlib/libc/sys/linux/include/netinet6/esp_rijndael.h newlib/libc/sys/linux/include/netinet6/icmp6.h newlib/libc/sys/linux/include/netinet6/in6.h newlib/libc/sys/linux/include/netinet6/in6_gif.h newlib/libc/sys/linux/include/netinet6/in6_ifattach.h newlib/libc/sys/linux/include/netinet6/in6_pcb.h newlib/libc/sys/linux/include/netinet6/in6_prefix.h newlib/libc/sys/linux/include/netinet6/in6_var.h newlib/libc/sys/linux/include/netinet6/ip6.h newlib/libc/sys/linux/include/netinet6/ip6_ecn.h newlib/libc/sys/linux/include/netinet6/ip6_fw.h newlib/libc/sys/linux/include/netinet6/ip6_mroute.h newlib/libc/sys/linux/include/netinet6/ip6_var.h newlib/libc/sys/linux/include/netinet6/ip6protosw.h newlib/libc/sys/linux/include/netinet6/ipcomp.h newlib/libc/sys/linux/include/netinet6/ipcomp6.h newlib/libc/sys/linux/include/netinet6/ipsec.h newlib/libc/sys/linux/include/netinet6/ipsec6.h newlib/libc/sys/linux/include/netinet6/mld6_var.h newlib/libc/sys/linux/include/netinet6/nd6.h newlib/libc/sys/linux/include/netinet6/pim6.h newlib/libc/sys/linux/include/netinet6/pim6_var.h newlib/libc/sys/linux/include/netinet6/raw_ip6.h newlib/libc/sys/linux/include/netinet6/scope6_var.h newlib/libc/sys/linux/include/netinet6/tcp6_var.h newlib/libc/sys/linux/include/netinet6/udp6_var.h newlib/libc/sys/linux/include/netns/idp.h newlib/libc/sys/linux/include/netns/idp_var.h newlib/libc/sys/linux/include/netns/ns.h newlib/libc/sys/linux/include/netns/ns_error.h newlib/libc/sys/linux/include/netns/ns_if.h newlib/libc/sys/linux/include/netns/ns_pcb.h newlib/libc/sys/linux/include/netns/sp.h newlib/libc/sys/linux/include/netns/spidp.h newlib/libc/sys/linux/include/netns/spp_debug.h newlib/libc/sys/linux/include/netns/spp_timer.h newlib/libc/sys/linux/include/netns/spp_var.h newlib/libc/sys/linux/include/paths.h newlib/libc/sys/linux/include/pthread.h newlib/libc/sys/linux/include/regex.h newlib/libc/sys/linux/include/resolv.h newlib/libc/sys/linux/include/rpc/Makefile newlib/libc/sys/linux/include/rpc/auth.h newlib/libc/sys/linux/include/rpc/auth_des.h newlib/libc/sys/linux/include/rpc/auth_kerb.h newlib/libc/sys/linux/include/rpc/auth_unix.h newlib/libc/sys/linux/include/rpc/clnt.h newlib/libc/sys/linux/include/rpc/clnt_soc.h newlib/libc/sys/linux/include/rpc/clnt_stat.h newlib/libc/sys/linux/include/rpc/des.h newlib/libc/sys/linux/include/rpc/des_crypt.h newlib/libc/sys/linux/include/rpc/nettype.h newlib/libc/sys/linux/include/rpc/pmap_clnt.h newlib/libc/sys/linux/include/rpc/pmap_prot.h newlib/libc/sys/linux/include/rpc/pmap_rmt.h newlib/libc/sys/linux/include/rpc/raw.h newlib/libc/sys/linux/include/rpc/rpc.h newlib/libc/sys/linux/include/rpc/rpc_com.h newlib/libc/sys/linux/include/rpc/rpc_msg.h newlib/libc/sys/linux/include/rpc/rpcb_clnt.h newlib/libc/sys/linux/include/rpc/rpcb_prot.h newlib/libc/sys/linux/include/rpc/rpcb_prot.x newlib/libc/sys/linux/include/rpc/rpcent.h newlib/libc/sys/linux/include/rpc/svc.h newlib/libc/sys/linux/include/rpc/svc_auth.h newlib/libc/sys/linux/include/rpc/svc_dg.h newlib/libc/sys/linux/include/rpc/svc_soc.h newlib/libc/sys/linux/include/rpc/types.h newlib/libc/sys/linux/include/rpc/xdr.h newlib/libc/sys/linux/include/rune.h newlib/libc/sys/linux/include/runetype.h newlib/libc/sys/linux/include/sched.h newlib/libc/sys/linux/include/semaphore.h newlib/libc/sys/linux/include/setjmp.h newlib/libc/sys/linux/include/setlocale.h newlib/libc/sys/linux/include/stdint.h newlib/libc/sys/linux/include/time.h newlib/libc/sys/linux/include/un-namespace.h newlib/libc/sys/linux/include/unistd.h newlib/libc/sys/linux/include/wordexp.h newlib/libc/sys/linux/inode.c newlib/libc/sys/linux/internal_statvfs.c newlib/libc/sys/linux/intl/Makefile.am newlib/libc/sys/linux/intl/Makefile.in newlib/libc/sys/linux/intl/bindtextdom.c newlib/libc/sys/linux/intl/catgets.c newlib/libc/sys/linux/intl/catgetsinfo.h newlib/libc/sys/linux/intl/config.h newlib/libc/sys/linux/intl/dcgettext.c newlib/libc/sys/linux/intl/dcigettext.c newlib/libc/sys/linux/intl/dcngettext.c newlib/libc/sys/linux/intl/dgettext.c newlib/libc/sys/linux/intl/dngettext.c newlib/libc/sys/linux/intl/explodename.c newlib/libc/sys/linux/intl/finddomain.c newlib/libc/sys/linux/intl/gettext.c newlib/libc/sys/linux/intl/gettext.h newlib/libc/sys/linux/intl/gettextP.h newlib/libc/sys/linux/intl/hash-string.h newlib/libc/sys/linux/intl/l10nflist.c newlib/libc/sys/linux/intl/lcl_stpcpy.c newlib/libc/sys/linux/intl/loadinfo.h newlib/libc/sys/linux/intl/loadmsgcat.c newlib/libc/sys/linux/intl/localealias.c newlib/libc/sys/linux/intl/ngettext.c newlib/libc/sys/linux/intl/open_catalog.c newlib/libc/sys/linux/intl/plural.c newlib/libc/sys/linux/intl/plural.y newlib/libc/sys/linux/intl/textdomain.c newlib/libc/sys/linux/io.c newlib/libc/sys/linux/io64.c newlib/libc/sys/linux/ipc.c newlib/libc/sys/linux/isatty.c newlib/libc/sys/linux/kernel_sigaction.h newlib/libc/sys/linux/libc-internal.h newlib/libc/sys/linux/libc-symbols.h newlib/libc/sys/linux/libc-tsd.h newlib/libc/sys/linux/libintl.h newlib/libc/sys/linux/linux.c newlib/libc/sys/linux/linux_fsinfo.h newlib/libc/sys/linux/linuxthreads/LICENSE newlib/libc/sys/linux/linuxthreads/Makefile.am newlib/libc/sys/linux/linuxthreads/Makefile.in newlib/libc/sys/linux/linuxthreads/aclocal.m4 newlib/libc/sys/linux/linuxthreads/attr.c newlib/libc/sys/linux/linuxthreads/barrier.c newlib/libc/sys/linux/linuxthreads/bits/initspin.h newlib/libc/sys/linux/linuxthreads/bits/libc-lock.h newlib/libc/sys/linux/linuxthreads/bits/libc-tsd.h newlib/libc/sys/linux/linuxthreads/bits/local_lim.h newlib/libc/sys/linux/linuxthreads/bits/posix_opt.h newlib/libc/sys/linux/linuxthreads/bits/pthreadtypes.h newlib/libc/sys/linux/linuxthreads/bits/sigthread.h newlib/libc/sys/linux/linuxthreads/bp-sym.h newlib/libc/sys/linux/linuxthreads/cancel.c newlib/libc/sys/linux/linuxthreads/condvar.c newlib/libc/sys/linux/linuxthreads/config.h newlib/libc/sys/linux/linuxthreads/configure newlib/libc/sys/linux/linuxthreads/configure.in newlib/libc/sys/linux/linuxthreads/defs.awk newlib/libc/sys/linux/linuxthreads/ecmutex.c newlib/libc/sys/linux/linuxthreads/events.c newlib/libc/sys/linux/linuxthreads/getcpuclockid.c newlib/libc/sys/linux/linuxthreads/getreent.c newlib/libc/sys/linux/linuxthreads/internals.h newlib/libc/sys/linux/linuxthreads/join.c newlib/libc/sys/linux/linuxthreads/joinrace.c newlib/libc/sys/linux/linuxthreads/kernel-features.h newlib/libc/sys/linux/linuxthreads/libc-internal.h newlib/libc/sys/linux/linuxthreads/libc-symbols.h newlib/libc/sys/linux/linuxthreads/linuxthreads.texi newlib/libc/sys/linux/linuxthreads/lockfile.c newlib/libc/sys/linux/linuxthreads/machine/Makefile.am newlib/libc/sys/linux/linuxthreads/machine/Makefile.in newlib/libc/sys/linux/linuxthreads/machine/aclocal.m4 newlib/libc/sys/linux/linuxthreads/machine/configure newlib/libc/sys/linux/linuxthreads/machine/configure.in newlib/libc/sys/linux/linuxthreads/machine/generic/generic-sysdep.h newlib/libc/sys/linux/linuxthreads/machine/i386/Makefile.am newlib/libc/sys/linux/linuxthreads/machine/i386/Makefile.in newlib/libc/sys/linux/linuxthreads/machine/i386/aclocal.m4 newlib/libc/sys/linux/linuxthreads/machine/i386/bp-asm.h newlib/libc/sys/linux/linuxthreads/machine/i386/clone.S newlib/libc/sys/linux/linuxthreads/machine/i386/configure newlib/libc/sys/linux/linuxthreads/machine/i386/configure.in newlib/libc/sys/linux/linuxthreads/machine/i386/i386-sysdep.S newlib/libc/sys/linux/linuxthreads/machine/i386/i386-sysdep.h newlib/libc/sys/linux/linuxthreads/machine/i386/pspinlock.c newlib/libc/sys/linux/linuxthreads/machine/i386/pt-machine.h newlib/libc/sys/linux/linuxthreads/machine/i386/sigcontextinfo.h newlib/libc/sys/linux/linuxthreads/machine/i386/stackinfo.h newlib/libc/sys/linux/linuxthreads/machine/i386/sysdep.S newlib/libc/sys/linux/linuxthreads/machine/i386/sysdep.h newlib/libc/sys/linux/linuxthreads/machine/i386/useldt.h newlib/libc/sys/linux/linuxthreads/manager.c newlib/libc/sys/linux/linuxthreads/mq_notify.c newlib/libc/sys/linux/linuxthreads/mutex.c newlib/libc/sys/linux/linuxthreads/no-tsd.c newlib/libc/sys/linux/linuxthreads/oldsemaphore.c newlib/libc/sys/linux/linuxthreads/posix-timer.h newlib/libc/sys/linux/linuxthreads/prio.c newlib/libc/sys/linux/linuxthreads/proc_service.h newlib/libc/sys/linux/linuxthreads/pt-machine.c newlib/libc/sys/linux/linuxthreads/ptclock_gettime.c newlib/libc/sys/linux/linuxthreads/ptclock_settime.c newlib/libc/sys/linux/linuxthreads/ptfork.c newlib/libc/sys/linux/linuxthreads/pthread.c newlib/libc/sys/linux/linuxthreads/ptlongjmp.c newlib/libc/sys/linux/linuxthreads/queue.h newlib/libc/sys/linux/linuxthreads/reent.c newlib/libc/sys/linux/linuxthreads/reqsyscalls.c newlib/libc/sys/linux/linuxthreads/restart.h newlib/libc/sys/linux/linuxthreads/rwlock.c newlib/libc/sys/linux/linuxthreads/semaphore.c newlib/libc/sys/linux/linuxthreads/semaphore.h newlib/libc/sys/linux/linuxthreads/shlib-compat.h newlib/libc/sys/linux/linuxthreads/signals.c newlib/libc/sys/linux/linuxthreads/specific.c newlib/libc/sys/linux/linuxthreads/spinlock.c newlib/libc/sys/linux/linuxthreads/spinlock.h newlib/libc/sys/linux/linuxthreads/sysctl.c newlib/libc/sys/linux/linuxthreads/td_init.c newlib/libc/sys/linux/linuxthreads/td_log.c newlib/libc/sys/linux/linuxthreads/td_symbol_list.c newlib/libc/sys/linux/linuxthreads/td_ta_clear_event.c newlib/libc/sys/linux/linuxthreads/td_ta_delete.c newlib/libc/sys/linux/linuxthreads/td_ta_enable_stats.c newlib/libc/sys/linux/linuxthreads/td_ta_event_addr.c newlib/libc/sys/linux/linuxthreads/td_ta_event_getmsg.c newlib/libc/sys/linux/linuxthreads/td_ta_get_nthreads.c newlib/libc/sys/linux/linuxthreads/td_ta_get_ph.c newlib/libc/sys/linux/linuxthreads/td_ta_get_stats.c newlib/libc/sys/linux/linuxthreads/td_ta_map_id2thr.c newlib/libc/sys/linux/linuxthreads/td_ta_map_lwp2thr.c newlib/libc/sys/linux/linuxthreads/td_ta_new.c newlib/libc/sys/linux/linuxthreads/td_ta_reset_stats.c newlib/libc/sys/linux/linuxthreads/td_ta_set_event.c newlib/libc/sys/linux/linuxthreads/td_ta_setconcurrency.c newlib/libc/sys/linux/linuxthreads/td_ta_thr_iter.c newlib/libc/sys/linux/linuxthreads/td_ta_tsd_iter.c newlib/libc/sys/linux/linuxthreads/td_thr_clear_event.c newlib/libc/sys/linux/linuxthreads/td_thr_dbresume.c newlib/libc/sys/linux/linuxthreads/td_thr_dbsuspend.c newlib/libc/sys/linux/linuxthreads/td_thr_event_enable.c newlib/libc/sys/linux/linuxthreads/td_thr_event_getmsg.c newlib/libc/sys/linux/linuxthreads/td_thr_get_info.c newlib/libc/sys/linux/linuxthreads/td_thr_getfpregs.c newlib/libc/sys/linux/linuxthreads/td_thr_getgregs.c newlib/libc/sys/linux/linuxthreads/td_thr_getxregs.c newlib/libc/sys/linux/linuxthreads/td_thr_getxregsize.c newlib/libc/sys/linux/linuxthreads/td_thr_set_event.c newlib/libc/sys/linux/linuxthreads/td_thr_setfpregs.c newlib/libc/sys/linux/linuxthreads/td_thr_setgregs.c newlib/libc/sys/linux/linuxthreads/td_thr_setprio.c newlib/libc/sys/linux/linuxthreads/td_thr_setsigpending.c newlib/libc/sys/linux/linuxthreads/td_thr_setxregs.c newlib/libc/sys/linux/linuxthreads/td_thr_sigsetmask.c newlib/libc/sys/linux/linuxthreads/td_thr_tsd.c newlib/libc/sys/linux/linuxthreads/td_thr_validate.c newlib/libc/sys/linux/linuxthreads/testrtsig.h newlib/libc/sys/linux/linuxthreads/thread_db.h newlib/libc/sys/linux/linuxthreads/thread_dbP.h newlib/libc/sys/linux/linuxthreads/timer_create.c newlib/libc/sys/linux/linuxthreads/timer_delete.c newlib/libc/sys/linux/linuxthreads/timer_getoverr.c newlib/libc/sys/linux/linuxthreads/timer_gettime.c newlib/libc/sys/linux/linuxthreads/timer_routines.c newlib/libc/sys/linux/linuxthreads/timer_settime.c newlib/libc/sys/linux/linuxthreads/tst-cancel.c newlib/libc/sys/linux/linuxthreads/tst-context.c newlib/libc/sys/linux/linuxthreads/tststack.c newlib/libc/sys/linux/linuxthreads/unload.c newlib/libc/sys/linux/linuxthreads/weaks.c newlib/libc/sys/linux/linuxthreads/wrapsyscall.c newlib/libc/sys/linux/machine/Makefile.am newlib/libc/sys/linux/machine/Makefile.in newlib/libc/sys/linux/machine/aclocal.m4 newlib/libc/sys/linux/machine/configure newlib/libc/sys/linux/machine/configure.in newlib/libc/sys/linux/machine/hp-timing.h newlib/libc/sys/linux/machine/i386/Makefile.am newlib/libc/sys/linux/machine/i386/Makefile.in newlib/libc/sys/linux/machine/i386/aclocal.m4 newlib/libc/sys/linux/machine/i386/atomic.h newlib/libc/sys/linux/machine/i386/configure newlib/libc/sys/linux/machine/i386/configure.in newlib/libc/sys/linux/machine/i386/crt0.c newlib/libc/sys/linux/machine/i386/dl-machine.h newlib/libc/sys/linux/machine/i386/dl-procinfo.c newlib/libc/sys/linux/machine/i386/dl-procinfo.h newlib/libc/sys/linux/machine/i386/get_clockfreq.c newlib/libc/sys/linux/machine/i386/getpagesize.c newlib/libc/sys/linux/machine/i386/hp-timing.c newlib/libc/sys/linux/machine/i386/hp-timing.h newlib/libc/sys/linux/machine/i386/huge_val.h newlib/libc/sys/linux/machine/i386/i386mach.h newlib/libc/sys/linux/machine/i386/include/endian.h newlib/libc/sys/linux/machine/i386/include/param.h newlib/libc/sys/linux/machine/i386/include/setjmp.h newlib/libc/sys/linux/machine/i386/include/termios.h newlib/libc/sys/linux/machine/i386/setjmp.S newlib/libc/sys/linux/machine/i386/sigaction.c newlib/libc/sys/linux/machine/i386/sigstack.h newlib/libc/sys/linux/machine/i386/socketcall.h newlib/libc/sys/linux/machine/i386/syscall.h newlib/libc/sys/linux/machine/i386/sysdep.h newlib/libc/sys/linux/machine/i386/weakalias.h newlib/libc/sys/linux/malign.c newlib/libc/sys/linux/malignr.c newlib/libc/sys/linux/mallinfor.c newlib/libc/sys/linux/malloc.c newlib/libc/sys/linux/mallocr.c newlib/libc/sys/linux/malloptr.c newlib/libc/sys/linux/mallstatsr.c newlib/libc/sys/linux/mcheck.c newlib/libc/sys/linux/mhooks.h newlib/libc/sys/linux/mmap.c newlib/libc/sys/linux/mntent.c newlib/libc/sys/linux/mntent_r.c newlib/libc/sys/linux/mq_close.c newlib/libc/sys/linux/mq_getattr.c newlib/libc/sys/linux/mq_notify.c newlib/libc/sys/linux/mq_open.c newlib/libc/sys/linux/mq_receive.c newlib/libc/sys/linux/mq_send.c newlib/libc/sys/linux/mq_setattr.c newlib/libc/sys/linux/mq_unlink.c newlib/libc/sys/linux/mqlocal.h newlib/libc/sys/linux/msize.c newlib/libc/sys/linux/msizer.c newlib/libc/sys/linux/mstats.c newlib/libc/sys/linux/mtrim.c newlib/libc/sys/linux/mtrimr.c newlib/libc/sys/linux/net/Makefile.am newlib/libc/sys/linux/net/Makefile.in newlib/libc/sys/linux/net/XXX-lookup.c newlib/libc/sys/linux/net/addr2ascii.c newlib/libc/sys/linux/net/alias-lookup.c newlib/libc/sys/linux/net/aliases.h newlib/libc/sys/linux/net/ascii2addr.c newlib/libc/sys/linux/net/base64.c newlib/libc/sys/linux/net/check_pf.c newlib/libc/sys/linux/net/databases.def newlib/libc/sys/linux/net/digits_dots.c newlib/libc/sys/linux/net/ether_aton.c newlib/libc/sys/linux/net/ether_aton_r.c newlib/libc/sys/linux/net/ether_hton.c newlib/libc/sys/linux/net/ether_line.c newlib/libc/sys/linux/net/ether_ntoa.c newlib/libc/sys/linux/net/ether_ntoa_r.c newlib/libc/sys/linux/net/ether_ntoh.c newlib/libc/sys/linux/net/etherent.h newlib/libc/sys/linux/net/ethers-lookup.c newlib/libc/sys/linux/net/function.def newlib/libc/sys/linux/net/getXXbyYY.c newlib/libc/sys/linux/net/getXXbyYY_r.c newlib/libc/sys/linux/net/getXXent.c newlib/libc/sys/linux/net/getXXent_r.c newlib/libc/sys/linux/net/getaddrinfo.c newlib/libc/sys/linux/net/getaliasent.c newlib/libc/sys/linux/net/getaliasent_r.c newlib/libc/sys/linux/net/getaliasname.c newlib/libc/sys/linux/net/getaliasname_r.c newlib/libc/sys/linux/net/gethstbyad.c newlib/libc/sys/linux/net/gethstbyad_r.c newlib/libc/sys/linux/net/gethstbynm.c newlib/libc/sys/linux/net/gethstbynm2.c newlib/libc/sys/linux/net/gethstbynm2_r.c newlib/libc/sys/linux/net/gethstbynm_r.c newlib/libc/sys/linux/net/gethstent.c newlib/libc/sys/linux/net/gethstent_r.c newlib/libc/sys/linux/net/getnameinfo.c newlib/libc/sys/linux/net/getnetbyad.c newlib/libc/sys/linux/net/getnetbyad_r.c newlib/libc/sys/linux/net/getnetbynm.c newlib/libc/sys/linux/net/getnetbynm_r.c newlib/libc/sys/linux/net/getnetent.c newlib/libc/sys/linux/net/getnetent_r.c newlib/libc/sys/linux/net/getnetgrent.c newlib/libc/sys/linux/net/getnetgrent_r.c newlib/libc/sys/linux/net/getnssent.c newlib/libc/sys/linux/net/getnssent_r.c newlib/libc/sys/linux/net/getproto.c newlib/libc/sys/linux/net/getproto_r.c newlib/libc/sys/linux/net/getprtent.c newlib/libc/sys/linux/net/getprtent_r.c newlib/libc/sys/linux/net/getprtname.c newlib/libc/sys/linux/net/getprtname_r.c newlib/libc/sys/linux/net/getrpcbyname.c newlib/libc/sys/linux/net/getrpcbyname_r.c newlib/libc/sys/linux/net/getrpcbynumber.c newlib/libc/sys/linux/net/getrpcbynumber_r.c newlib/libc/sys/linux/net/getrpcent.c newlib/libc/sys/linux/net/getrpcent_r.c newlib/libc/sys/linux/net/getservent.c newlib/libc/sys/linux/net/getservent_r.c newlib/libc/sys/linux/net/getsrvbynm.c newlib/libc/sys/linux/net/getsrvbynm_r.c newlib/libc/sys/linux/net/getsrvbypt.c newlib/libc/sys/linux/net/getsrvbypt_r.c newlib/libc/sys/linux/net/grp-lookup.c newlib/libc/sys/linux/net/herrno.c newlib/libc/sys/linux/net/hosts-lookup.c newlib/libc/sys/linux/net/ifaddrs.h newlib/libc/sys/linux/net/ifname.c newlib/libc/sys/linux/net/ifreq.c newlib/libc/sys/linux/net/ifreq.h newlib/libc/sys/linux/net/in6_addr.c newlib/libc/sys/linux/net/inet6_option.c newlib/libc/sys/linux/net/inet_addr.c newlib/libc/sys/linux/net/inet_lnaof.c newlib/libc/sys/linux/net/inet_mkadr.c newlib/libc/sys/linux/net/inet_net.c newlib/libc/sys/linux/net/inet_net_ntop.c newlib/libc/sys/linux/net/inet_net_pton.c newlib/libc/sys/linux/net/inet_neta.c newlib/libc/sys/linux/net/inet_netof.c newlib/libc/sys/linux/net/inet_ntoa.c newlib/libc/sys/linux/net/inet_ntop.c newlib/libc/sys/linux/net/inet_pton.c newlib/libc/sys/linux/net/issetugid-stub.c newlib/libc/sys/linux/net/key-lookup.c newlib/libc/sys/linux/net/local.h newlib/libc/sys/linux/net/netgroup.h newlib/libc/sys/linux/net/netgrp-lookup.c newlib/libc/sys/linux/net/network-lookup.c newlib/libc/sys/linux/net/not-cancel.h newlib/libc/sys/linux/net/ns_name.c newlib/libc/sys/linux/net/ns_netint.c newlib/libc/sys/linux/net/ns_parse.c newlib/libc/sys/linux/net/ns_print.c newlib/libc/sys/linux/net/ns_samedomain.c newlib/libc/sys/linux/net/ns_ttl.c newlib/libc/sys/linux/net/nsap_addr.c newlib/libc/sys/linux/net/nscd-types.h newlib/libc/sys/linux/net/nscd/nscd-client.h newlib/libc/sys/linux/net/nscd/nscd_proto.h newlib/libc/sys/linux/net/nss.h newlib/libc/sys/linux/net/nsswitch.c newlib/libc/sys/linux/net/nsswitch.h newlib/libc/sys/linux/net/opensock.c newlib/libc/sys/linux/net/proto-lookup.c newlib/libc/sys/linux/net/pwd-lookup.c newlib/libc/sys/linux/net/rcmd.c newlib/libc/sys/linux/net/rcmdsh.c newlib/libc/sys/linux/net/recv.c newlib/libc/sys/linux/net/res_comp.c newlib/libc/sys/linux/net/res_data.c newlib/libc/sys/linux/net/res_debug.c newlib/libc/sys/linux/net/res_debug.h newlib/libc/sys/linux/net/res_hconf.c newlib/libc/sys/linux/net/res_hconf.h newlib/libc/sys/linux/net/res_init.c newlib/libc/sys/linux/net/res_libc.c newlib/libc/sys/linux/net/res_mkquery.c newlib/libc/sys/linux/net/res_query.c newlib/libc/sys/linux/net/res_send.c newlib/libc/sys/linux/net/rexec.c newlib/libc/sys/linux/net/rpc-lookup.c newlib/libc/sys/linux/net/ruserpass.c newlib/libc/sys/linux/net/send.c newlib/libc/sys/linux/net/service-lookup.c newlib/libc/sys/linux/net/spwd-lookup.c newlib/libc/sys/linux/net/un-namespace.h newlib/libc/sys/linux/ntp_gettime.c newlib/libc/sys/linux/pathconf.c newlib/libc/sys/linux/pread.c newlib/libc/sys/linux/pread64.c newlib/libc/sys/linux/process.c newlib/libc/sys/linux/prof-freq.c newlib/libc/sys/linux/profile.c newlib/libc/sys/linux/psignal.c newlib/libc/sys/linux/pvallocr.c newlib/libc/sys/linux/pwrite.c newlib/libc/sys/linux/pwrite64.c newlib/libc/sys/linux/raise.c newlib/libc/sys/linux/readdir64.c newlib/libc/sys/linux/realloc.c newlib/libc/sys/linux/reallocr.c newlib/libc/sys/linux/realpath.c newlib/libc/sys/linux/rename.c newlib/libc/sys/linux/resource.c newlib/libc/sys/linux/scandir64.c newlib/libc/sys/linux/sched.c newlib/libc/sys/linux/select.c newlib/libc/sys/linux/seteuid.c newlib/libc/sys/linux/sethostid.c newlib/libc/sys/linux/sethostname.c newlib/libc/sys/linux/setrlimit64.c newlib/libc/sys/linux/shared.ld newlib/libc/sys/linux/shlib-compat.h newlib/libc/sys/linux/shm_open.c newlib/libc/sys/linux/shm_unlink.c newlib/libc/sys/linux/sig.c newlib/libc/sys/linux/sigaction.c newlib/libc/sys/linux/siglongjmp.c newlib/libc/sys/linux/signal.c newlib/libc/sys/linux/sigqueue.c newlib/libc/sys/linux/sigset.c newlib/libc/sys/linux/sigwait.c newlib/libc/sys/linux/sleep.c newlib/libc/sys/linux/socket.c newlib/libc/sys/linux/sockops.h newlib/libc/sys/linux/stack.c newlib/libc/sys/linux/statvfs.c newlib/libc/sys/linux/statvfs64.c newlib/libc/sys/linux/strsignal.c newlib/libc/sys/linux/strverscmp.c newlib/libc/sys/linux/sys/_types.h newlib/libc/sys/linux/sys/cdefs.h newlib/libc/sys/linux/sys/dirent.h newlib/libc/sys/linux/sys/dlfcn.h newlib/libc/sys/linux/sys/elfclass.h newlib/libc/sys/linux/sys/errno.h newlib/libc/sys/linux/sys/event.h newlib/libc/sys/linux/sys/fcntl.h newlib/libc/sys/linux/sys/features.h newlib/libc/sys/linux/sys/file.h newlib/libc/sys/linux/sys/ioccom.h newlib/libc/sys/linux/sys/ioctl.h newlib/libc/sys/linux/sys/libc-lock.h newlib/libc/sys/linux/sys/libc-tsd.h newlib/libc/sys/linux/sys/link.h newlib/libc/sys/linux/sys/linux_time.h newlib/libc/sys/linux/sys/lock.h newlib/libc/sys/linux/sys/param.h newlib/libc/sys/linux/sys/resource.h newlib/libc/sys/linux/sys/select.h newlib/libc/sys/linux/sys/signal.h newlib/libc/sys/linux/sys/socket.h newlib/libc/sys/linux/sys/sockio.h newlib/libc/sys/linux/sys/stat.h newlib/libc/sys/linux/sys/stdint.h newlib/libc/sys/linux/sys/stdio.h newlib/libc/sys/linux/sys/string.h newlib/libc/sys/linux/sys/termios.h newlib/libc/sys/linux/sys/time.h newlib/libc/sys/linux/sys/types.h newlib/libc/sys/linux/sys/unistd.h newlib/libc/sys/linux/sys/utime.h newlib/libc/sys/linux/sys/utmp.h newlib/libc/sys/linux/sys/utsname.h newlib/libc/sys/linux/sys/wait.h newlib/libc/sys/linux/sysconf.c newlib/libc/sys/linux/sysctl.c newlib/libc/sys/linux/systat.c newlib/libc/sys/linux/system.c newlib/libc/sys/linux/tcdrain.c newlib/libc/sys/linux/tcsendbrk.c newlib/libc/sys/linux/termios.c newlib/libc/sys/linux/thread-m.h newlib/libc/sys/linux/time.c newlib/libc/sys/linux/ttyname_r.c newlib/libc/sys/linux/usleep.c newlib/libc/sys/linux/utimes.c newlib/libc/sys/linux/vallocr.c newlib/libc/sys/linux/versionsort.c newlib/libc/sys/linux/versionsort64.c newlib/libc/sys/linux/wait.c newlib/libc/sys/m88kbug/Makefile.am newlib/libc/sys/m88kbug/Makefile.in newlib/libc/sys/m88kbug/aclocal.m4 newlib/libc/sys/m88kbug/configure newlib/libc/sys/m88kbug/configure.in newlib/libc/sys/m88kbug/crt0.c newlib/libc/sys/m88kbug/sys/systraps.h newlib/libc/sys/m88kbug/syscalls.c newlib/libc/sys/mmixware/Makefile.am newlib/libc/sys/mmixware/Makefile.in newlib/libc/sys/mmixware/_exit.c newlib/libc/sys/mmixware/access.c newlib/libc/sys/mmixware/aclocal.m4 newlib/libc/sys/mmixware/chmod.c newlib/libc/sys/mmixware/chown.c newlib/libc/sys/mmixware/close.c newlib/libc/sys/mmixware/configure newlib/libc/sys/mmixware/configure.in newlib/libc/sys/mmixware/creat.c newlib/libc/sys/mmixware/crt0.c newlib/libc/sys/mmixware/execv.c newlib/libc/sys/mmixware/execve.c newlib/libc/sys/mmixware/fork.c newlib/libc/sys/mmixware/fstat.c newlib/libc/sys/mmixware/getpid.c newlib/libc/sys/mmixware/gettime.c newlib/libc/sys/mmixware/isatty.c newlib/libc/sys/mmixware/kill.c newlib/libc/sys/mmixware/link.c newlib/libc/sys/mmixware/lseek.c newlib/libc/sys/mmixware/open.c newlib/libc/sys/mmixware/pipe.c newlib/libc/sys/mmixware/read.c newlib/libc/sys/mmixware/sbrk.c newlib/libc/sys/mmixware/setjmp.S newlib/libc/sys/mmixware/stat.c newlib/libc/sys/mmixware/sys/syscall.h newlib/libc/sys/mmixware/time.c newlib/libc/sys/mmixware/times.c newlib/libc/sys/mmixware/unlink.c newlib/libc/sys/mmixware/utime.c newlib/libc/sys/mmixware/wait.c newlib/libc/sys/mmixware/write.c newlib/libc/sys/netware/Makefile.am newlib/libc/sys/netware/Makefile.in newlib/libc/sys/netware/aclocal.m4 newlib/libc/sys/netware/configure newlib/libc/sys/netware/configure.in newlib/libc/sys/netware/crt0.c newlib/libc/sys/netware/getpid.c newlib/libc/sys/netware/link.c newlib/libc/sys/rdos/Makefile.am newlib/libc/sys/rdos/Makefile.in newlib/libc/sys/rdos/aclocal.m4 newlib/libc/sys/rdos/chown.c newlib/libc/sys/rdos/close.c newlib/libc/sys/rdos/config.h newlib/libc/sys/rdos/configure newlib/libc/sys/rdos/configure.in newlib/libc/sys/rdos/crt0.S newlib/libc/sys/rdos/execve.c newlib/libc/sys/rdos/fork.c newlib/libc/sys/rdos/fstat.c newlib/libc/sys/rdos/getenv.c newlib/libc/sys/rdos/getpid.c newlib/libc/sys/rdos/gettod.c newlib/libc/sys/rdos/isatty.c newlib/libc/sys/rdos/kill.c newlib/libc/sys/rdos/link.c newlib/libc/sys/rdos/lseek.c newlib/libc/sys/rdos/open.c newlib/libc/sys/rdos/rdos.S newlib/libc/sys/rdos/rdos.h newlib/libc/sys/rdos/rdoshelp.c newlib/libc/sys/rdos/read.c newlib/libc/sys/rdos/readlink.c newlib/libc/sys/rdos/sbrk.c newlib/libc/sys/rdos/stat.c newlib/libc/sys/rdos/symlink.c newlib/libc/sys/rdos/times.c newlib/libc/sys/rdos/unlink.c newlib/libc/sys/rdos/user.def newlib/libc/sys/rdos/wait.c newlib/libc/sys/rdos/write.c newlib/libc/sys/rtems/Makefile.am newlib/libc/sys/rtems/Makefile.in newlib/libc/sys/rtems/aclocal.m4 newlib/libc/sys/rtems/configure newlib/libc/sys/rtems/configure.in newlib/libc/sys/rtems/crt0.c newlib/libc/sys/rtems/dummysys.c newlib/libc/sys/rtems/include/limits.h newlib/libc/sys/rtems/machine/limits.h newlib/libc/sys/rtems/machine/param.h newlib/libc/sys/rtems/sys/dirent.h newlib/libc/sys/rtems/sys/param.h newlib/libc/sys/rtems/sys/queue.h newlib/libc/sys/rtems/sys/syslimits.h newlib/libc/sys/rtems/sys/utime.h newlib/libc/sys/sh/Makefile.am newlib/libc/sys/sh/Makefile.in newlib/libc/sys/sh/aclocal.m4 newlib/libc/sys/sh/configure newlib/libc/sys/sh/configure.in newlib/libc/sys/sh/creat.c newlib/libc/sys/sh/crt0.S newlib/libc/sys/sh/ftruncate.c newlib/libc/sys/sh/sys/syscall.h newlib/libc/sys/sh/syscalls.c newlib/libc/sys/sh/trap.S newlib/libc/sys/sh/truncate.c newlib/libc/sys/sparc64/Makefile.am newlib/libc/sys/sparc64/Makefile.in newlib/libc/sys/sparc64/_exit.S newlib/libc/sys/sparc64/_main.c newlib/libc/sys/sparc64/aclocal.m4 newlib/libc/sys/sparc64/cerror.S newlib/libc/sys/sparc64/closedir.c newlib/libc/sys/sparc64/configure newlib/libc/sys/sparc64/configure.in newlib/libc/sys/sparc64/creat.c newlib/libc/sys/sparc64/crt0.S newlib/libc/sys/sparc64/dup2.S newlib/libc/sys/sparc64/execve.S newlib/libc/sys/sparc64/ieee.c newlib/libc/sys/sparc64/isatty.c newlib/libc/sys/sparc64/lstat.S newlib/libc/sys/sparc64/opendir.c newlib/libc/sys/sparc64/readdir.c newlib/libc/sys/sparc64/rewinddir.c newlib/libc/sys/sparc64/sbrk.S newlib/libc/sys/sparc64/scandir.c newlib/libc/sys/sparc64/seekdir.c newlib/libc/sys/sparc64/sigsetjmp.S newlib/libc/sys/sparc64/stat.S newlib/libc/sys/sparc64/sys/dirent.h newlib/libc/sys/sparc64/sys/fcntl.h newlib/libc/sys/sparc64/sys/file.h newlib/libc/sys/sparc64/sys/stat.h newlib/libc/sys/sparc64/sys/syscall.h newlib/libc/sys/sparc64/sys/syscallasm.h newlib/libc/sys/sparc64/sys/termios.h newlib/libc/sys/sparc64/sys/time.h newlib/libc/sys/sparc64/sys/utime.h newlib/libc/sys/sparc64/sys/utmp.h newlib/libc/sys/sparc64/sys/wait.h newlib/libc/sys/sparc64/telldir.c newlib/libc/sys/sparc64/template.S newlib/libc/sys/sparc64/template_r.S newlib/libc/sys/sparc64/utime.S newlib/libc/sys/sparc64/utime2.c newlib/libc/sys/sparc64/wait.S newlib/libc/sys/sun4/Makefile.am newlib/libc/sys/sun4/Makefile.in newlib/libc/sys/sun4/_main.c newlib/libc/sys/sun4/aclocal.m4 newlib/libc/sys/sun4/configure newlib/libc/sys/sun4/configure.in newlib/libc/sys/sun4/ieee.c newlib/libc/sys/sun4/sys/dirent.h newlib/libc/sys/sun4/sys/file.h newlib/libc/sys/sun4/sys/termios.h newlib/libc/sys/sun4/sys/utime.h newlib/libc/sys/sun4/sys/utmp.h newlib/libc/sys/sun4/sys/wait.h newlib/libc/sys/sysmec/Makefile.am newlib/libc/sys/sysmec/Makefile.in newlib/libc/sys/sysmec/_exit.c newlib/libc/sys/sysmec/access.c newlib/libc/sys/sysmec/aclocal.m4 newlib/libc/sys/sysmec/chmod.c newlib/libc/sys/sysmec/chown.c newlib/libc/sys/sysmec/close.c newlib/libc/sys/sysmec/configure newlib/libc/sys/sysmec/configure.in newlib/libc/sys/sysmec/creat.c newlib/libc/sys/sysmec/crt0.S newlib/libc/sys/sysmec/crt1.c newlib/libc/sys/sysmec/execv.c newlib/libc/sys/sysmec/execve.c newlib/libc/sys/sysmec/fork.c newlib/libc/sys/sysmec/fstat.c newlib/libc/sys/sysmec/getpid.c newlib/libc/sys/sysmec/gettime.c newlib/libc/sys/sysmec/isatty.c newlib/libc/sys/sysmec/kill.c newlib/libc/sys/sysmec/lseek.c newlib/libc/sys/sysmec/open.c newlib/libc/sys/sysmec/pipe.c newlib/libc/sys/sysmec/read.c newlib/libc/sys/sysmec/sbrk.c newlib/libc/sys/sysmec/stat.c newlib/libc/sys/sysmec/sys/syscall.h newlib/libc/sys/sysmec/time.c newlib/libc/sys/sysmec/times.c newlib/libc/sys/sysmec/trap.S newlib/libc/sys/sysmec/unlink.c newlib/libc/sys/sysmec/utime.c newlib/libc/sys/sysmec/wait.c newlib/libc/sys/sysmec/write.c newlib/libc/sys/sysnec810/Makefile.am newlib/libc/sys/sysnec810/Makefile.in newlib/libc/sys/sysnec810/aclocal.m4 newlib/libc/sys/sysnec810/configure newlib/libc/sys/sysnec810/configure.in newlib/libc/sys/sysnec810/crt0.S newlib/libc/sys/sysnec810/io.S newlib/libc/sys/sysnec810/misc.c newlib/libc/sys/sysnec810/sbrk.c newlib/libc/sys/sysnec810/write.c newlib/libc/sys/sysnecv850/Makefile.am newlib/libc/sys/sysnecv850/Makefile.in newlib/libc/sys/sysnecv850/_exit.c newlib/libc/sys/sysnecv850/access.c newlib/libc/sys/sysnecv850/aclocal.m4 newlib/libc/sys/sysnecv850/chmod.c newlib/libc/sys/sysnecv850/chown.c newlib/libc/sys/sysnecv850/close.c newlib/libc/sys/sysnecv850/configure newlib/libc/sys/sysnecv850/configure.in newlib/libc/sys/sysnecv850/creat.c newlib/libc/sys/sysnecv850/crt0.S newlib/libc/sys/sysnecv850/crt1.c newlib/libc/sys/sysnecv850/execv.c newlib/libc/sys/sysnecv850/execve.c newlib/libc/sys/sysnecv850/fork.c newlib/libc/sys/sysnecv850/fstat.c newlib/libc/sys/sysnecv850/getpid.c newlib/libc/sys/sysnecv850/gettime.c newlib/libc/sys/sysnecv850/isatty.c newlib/libc/sys/sysnecv850/kill.c newlib/libc/sys/sysnecv850/link.c newlib/libc/sys/sysnecv850/lseek.c newlib/libc/sys/sysnecv850/open.c newlib/libc/sys/sysnecv850/pipe.c newlib/libc/sys/sysnecv850/read.c newlib/libc/sys/sysnecv850/sbrk.c newlib/libc/sys/sysnecv850/stat.c newlib/libc/sys/sysnecv850/sys/syscall.h newlib/libc/sys/sysnecv850/time.c newlib/libc/sys/sysnecv850/times.c newlib/libc/sys/sysnecv850/trap.S newlib/libc/sys/sysnecv850/unlink.c newlib/libc/sys/sysnecv850/utime.c newlib/libc/sys/sysnecv850/wait.c newlib/libc/sys/sysnecv850/write.c newlib/libc/sys/sysvi386/Makefile.am newlib/libc/sys/sysvi386/Makefile.in newlib/libc/sys/sysvi386/_exit.S newlib/libc/sys/sysvi386/_longjmp.S newlib/libc/sys/sysvi386/_setjmp.S newlib/libc/sys/sysvi386/access.S newlib/libc/sys/sysvi386/aclocal.m4 newlib/libc/sys/sysvi386/alarm.S newlib/libc/sys/sysvi386/brk.S newlib/libc/sys/sysvi386/cerror.S newlib/libc/sys/sysvi386/chdir.S newlib/libc/sys/sysvi386/chmod.S newlib/libc/sys/sysvi386/close.S newlib/libc/sys/sysvi386/closedir.c newlib/libc/sys/sysvi386/configure newlib/libc/sys/sysvi386/configure.in newlib/libc/sys/sysvi386/crt0.c newlib/libc/sys/sysvi386/dup.c newlib/libc/sys/sysvi386/dup2.c newlib/libc/sys/sysvi386/exec.c newlib/libc/sys/sysvi386/execve.S newlib/libc/sys/sysvi386/fcntl.S newlib/libc/sys/sysvi386/fork.S newlib/libc/sys/sysvi386/fpathconf.S newlib/libc/sys/sysvi386/fps.S newlib/libc/sys/sysvi386/fpx.c newlib/libc/sys/sysvi386/fstat.S newlib/libc/sys/sysvi386/getdents.S newlib/libc/sys/sysvi386/getegid.S newlib/libc/sys/sysvi386/geteuid.S newlib/libc/sys/sysvi386/getgid.S newlib/libc/sys/sysvi386/getgroups.S newlib/libc/sys/sysvi386/getpid.S newlib/libc/sys/sysvi386/getuid.S newlib/libc/sys/sysvi386/ioctl.S newlib/libc/sys/sysvi386/isatty.c newlib/libc/sys/sysvi386/kill.S newlib/libc/sys/sysvi386/link.S newlib/libc/sys/sysvi386/lseek.S newlib/libc/sys/sysvi386/mkdir.S newlib/libc/sys/sysvi386/open.S newlib/libc/sys/sysvi386/opendir.c newlib/libc/sys/sysvi386/pathconf.S newlib/libc/sys/sysvi386/pause.S newlib/libc/sys/sysvi386/pipe.S newlib/libc/sys/sysvi386/read.S newlib/libc/sys/sysvi386/readdir.c newlib/libc/sys/sysvi386/rename.S newlib/libc/sys/sysvi386/rewinddir.c newlib/libc/sys/sysvi386/rmdir.S newlib/libc/sys/sysvi386/sbrk.c newlib/libc/sys/sysvi386/scandir.c newlib/libc/sys/sysvi386/seekdir.c newlib/libc/sys/sysvi386/setgid.S newlib/libc/sys/sysvi386/setuid.S newlib/libc/sys/sysvi386/sigaction.S newlib/libc/sys/sysvi386/signal.S newlib/libc/sys/sysvi386/sigprocmask.S newlib/libc/sys/sysvi386/sleep.c newlib/libc/sys/sysvi386/speed.c newlib/libc/sys/sysvi386/stat.S newlib/libc/sys/sysvi386/sys/dirent.h newlib/libc/sys/sysvi386/sys/setjmp.h newlib/libc/sys/sysvi386/sys/termio.h newlib/libc/sys/sysvi386/sys/termios.h newlib/libc/sys/sysvi386/sys/utime.h newlib/libc/sys/sysvi386/sys/utmp.h newlib/libc/sys/sysvi386/sys/wait.h newlib/libc/sys/sysvi386/sysconf.S newlib/libc/sys/sysvi386/tcgetattr.c newlib/libc/sys/sysvi386/tcline.c newlib/libc/sys/sysvi386/tcsetattr.c newlib/libc/sys/sysvi386/telldir.c newlib/libc/sys/sysvi386/time.S newlib/libc/sys/sysvi386/times.S newlib/libc/sys/sysvi386/unlink.S newlib/libc/sys/sysvi386/utime.S newlib/libc/sys/sysvi386/wait.S newlib/libc/sys/sysvi386/waitpid.S newlib/libc/sys/sysvi386/write.S newlib/libc/sys/sysvnecv70/Makefile.am newlib/libc/sys/sysvnecv70/Makefile.in newlib/libc/sys/sysvnecv70/aclocal.m4 newlib/libc/sys/sysvnecv70/cerror.S newlib/libc/sys/sysvnecv70/close.S newlib/libc/sys/sysvnecv70/configure newlib/libc/sys/sysvnecv70/configure.in newlib/libc/sys/sysvnecv70/crt0.S newlib/libc/sys/sysvnecv70/exit.S newlib/libc/sys/sysvnecv70/fps.S newlib/libc/sys/sysvnecv70/fpx.c newlib/libc/sys/sysvnecv70/fstat.S newlib/libc/sys/sysvnecv70/ioctl.S newlib/libc/sys/sysvnecv70/isatty.S newlib/libc/sys/sysvnecv70/lseek.S newlib/libc/sys/sysvnecv70/open.S newlib/libc/sys/sysvnecv70/read.S newlib/libc/sys/sysvnecv70/sbrk.S newlib/libc/sys/sysvnecv70/sysv60.S newlib/libc/sys/sysvnecv70/sysvnecv70.tex newlib/libc/sys/sysvnecv70/write.S newlib/libc/sys/tic80/Makefile.am newlib/libc/sys/tic80/Makefile.in newlib/libc/sys/tic80/aclocal.m4 newlib/libc/sys/tic80/configure newlib/libc/sys/tic80/configure.in newlib/libc/sys/tic80/crt0.c newlib/libc/sys/w65/Makefile.am newlib/libc/sys/w65/Makefile.in newlib/libc/sys/w65/aclocal.m4 newlib/libc/sys/w65/configure newlib/libc/sys/w65/configure.in newlib/libc/sys/w65/crt0.c newlib/libc/sys/w65/sys/syscall.h newlib/libc/sys/w65/syscalls.c newlib/libc/sys/w65/trap.c newlib/libc/sys/z8ksim/Makefile.am newlib/libc/sys/z8ksim/Makefile.in newlib/libc/sys/z8ksim/aclocal.m4 newlib/libc/sys/z8ksim/configure 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winsup/w32api/lib/extras-uuid.c winsup/w32api/lib/faultrep.def winsup/w32api/lib/gdi32.def winsup/w32api/lib/glaux.def winsup/w32api/lib/glu32.def winsup/w32api/lib/glut.def winsup/w32api/lib/glut32.def winsup/w32api/lib/hlguids-uuid.c winsup/w32api/lib/hlink-uuid.c winsup/w32api/lib/icmui.def winsup/w32api/lib/igmpagnt.def winsup/w32api/lib/imagehlp.def winsup/w32api/lib/imm32.def winsup/w32api/lib/iphlpapi.def winsup/w32api/lib/kernel32.def winsup/w32api/lib/largeint.c winsup/w32api/lib/lz32.def winsup/w32api/lib/mapi32.def winsup/w32api/lib/mfcuia32.def winsup/w32api/lib/mgmtapi.def winsup/w32api/lib/mlang-uuid.c winsup/w32api/lib/mpr.def winsup/w32api/lib/mprapi.def winsup/w32api/lib/mqrt.def winsup/w32api/lib/msacm32.def winsup/w32api/lib/mscms.def winsup/w32api/lib/mshtml-uuid.c winsup/w32api/lib/msimg32.def winsup/w32api/lib/msvcp60.def winsup/w32api/lib/msvfw32.def winsup/w32api/lib/mswsock.def winsup/w32api/lib/msxml-uuid.c winsup/w32api/lib/nddeapi.def winsup/w32api/lib/netapi32.def winsup/w32api/lib/ntdll.def winsup/w32api/lib/oaidl-uuid.c winsup/w32api/lib/objidl-uuid.c winsup/w32api/lib/objsafe-uuid.c winsup/w32api/lib/ocidl-uuid.c winsup/w32api/lib/odbc32.def winsup/w32api/lib/odbccp32.def winsup/w32api/lib/ole32.def winsup/w32api/lib/oleacc-uuid.c winsup/w32api/lib/oleacc.def winsup/w32api/lib/oleaut32.def winsup/w32api/lib/olecli32.def winsup/w32api/lib/olectlid-uuid.c winsup/w32api/lib/oledlg.def winsup/w32api/lib/oleidl-uuid.c winsup/w32api/lib/olepro32.def winsup/w32api/lib/olesvr32.def winsup/w32api/lib/opengl32.def winsup/w32api/lib/penwin32.def winsup/w32api/lib/pkpd32.def winsup/w32api/lib/power-uuid.c winsup/w32api/lib/powrprof.def winsup/w32api/lib/psapi.def winsup/w32api/lib/quartz.def winsup/w32api/lib/rapi.def winsup/w32api/lib/rasapi32.def winsup/w32api/lib/rasdlg.def winsup/w32api/lib/res.rc winsup/w32api/lib/rpcdce4.def winsup/w32api/lib/rpcns4.def winsup/w32api/lib/rpcrt4.def winsup/w32api/lib/rtm.def winsup/w32api/lib/rtutils.def winsup/w32api/lib/scrnsave.c winsup/w32api/lib/secur32.def winsup/w32api/lib/servprov-uuid.c winsup/w32api/lib/setupapi.def winsup/w32api/lib/shell32.c winsup/w32api/lib/shell32.def winsup/w32api/lib/shfolder.def winsup/w32api/lib/shlwapi.def winsup/w32api/lib/snmpapi.def winsup/w32api/lib/svrapi.def winsup/w32api/lib/tapi32.def winsup/w32api/lib/test.c winsup/w32api/lib/th32.def winsup/w32api/lib/thunk32.def winsup/w32api/lib/unknwn-uuid.c winsup/w32api/lib/url.def winsup/w32api/lib/urlmon-uuid.c winsup/w32api/lib/user32.def winsup/w32api/lib/userenv.def winsup/w32api/lib/usp10.def winsup/w32api/lib/uxtheme.def winsup/w32api/lib/vdmdbg.def winsup/w32api/lib/version.def winsup/w32api/lib/vfw32.mri winsup/w32api/lib/win32spl.def winsup/w32api/lib/wininet.def winsup/w32api/lib/winmm.def winsup/w32api/lib/winspool.def winsup/w32api/lib/winstrm.def winsup/w32api/lib/wldap32.def winsup/w32api/lib/wow32.def winsup/w32api/lib/ws2_32.c winsup/w32api/lib/ws2_32.def winsup/w32api/lib/wsnmp32.def winsup/w32api/lib/wsock32.def winsup/w32api/lib/wst.def winsup/w32api/lib/wtsapi32.def
author: cvs2svn <> 2008-11-19 18:25:20 +0000
committer: cvs2svn <> 2008-11-19 18:25:20 +0000
commit: ee40f8d491c436074cc576643f9d988b67319e8a (patch)
tree: 2497a7463a68744ea4f715f0ac57f7798813d92d /libgloss/bfin/include/defBF549.h
parent: 7562a08bb4d038699468d4c592a9f856f8e36c48 (diff)
download: cygnal-multiprocess-20081120-branchpoint.tar.gz
cygnal-multiprocess-20081120-branchpoint.tar.bz2
cygnal-multiprocess-20081120-branchpoint.zip
1 files changed, 0 insertions, 3449 deletions
diff --git a/libgloss/bfin/include/defBF549.h b/libgloss/bfin/include/defBF549.h
deleted file mode 100644
index aa81fb693..000000000
--- a/libgloss/bfin/include/defBF549.h
+++ /dev/null
@@ -1,3449 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF549.h
-**
-** Copyright (C) 2008 Analog Devices, Inc.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#endif /* _MISRA_RULES */
-
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <defBF54x_base.h>
-
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_THR  0xffc02128   /* Transmit Hold Register */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* MXVR Registers */
-
-#define                      MXVR_CONFIG  0xffc02700   /* MXVR Configuration Register */
-#define                     MXVR_STATE_0  0xffc02708   /* MXVR State Register 0 */
-#define                     MXVR_STATE_1  0xffc0270c   /* MXVR State Register 1 */
-#define                  MXVR_INT_STAT_0  0xffc02710   /* MXVR Interrupt Status Register 0 */
-#define                  MXVR_INT_STAT_1  0xffc02714   /* MXVR Interrupt Status Register 1 */
-#define                    MXVR_INT_EN_0  0xffc02718   /* MXVR Interrupt Enable Register 0 */
-#define                    MXVR_INT_EN_1  0xffc0271c   /* MXVR Interrupt Enable Register 1 */
-#define                    MXVR_POSITION  0xffc02720   /* MXVR Node Position Register */
-#define                MXVR_MAX_POSITION  0xffc02724   /* MXVR Maximum Node Position Register */
-#define                       MXVR_DELAY  0xffc02728   /* MXVR Node Frame Delay Register */
-#define                   MXVR_MAX_DELAY  0xffc0272c   /* MXVR Maximum Node Frame Delay Register */
-#define                       MXVR_LADDR  0xffc02730   /* MXVR Logical Address Register */
-#define                       MXVR_GADDR  0xffc02734   /* MXVR Group Address Register */
-#define                       MXVR_AADDR  0xffc02738   /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define                     MXVR_ALLOC_0  0xffc0273c   /* MXVR Allocation Table Register 0 */
-#define                     MXVR_ALLOC_1  0xffc02740   /* MXVR Allocation Table Register 1 */
-#define                     MXVR_ALLOC_2  0xffc02744   /* MXVR Allocation Table Register 2 */
-#define                     MXVR_ALLOC_3  0xffc02748   /* MXVR Allocation Table Register 3 */
-#define                     MXVR_ALLOC_4  0xffc0274c   /* MXVR Allocation Table Register 4 */
-#define                     MXVR_ALLOC_5  0xffc02750   /* MXVR Allocation Table Register 5 */
-#define                     MXVR_ALLOC_6  0xffc02754   /* MXVR Allocation Table Register 6 */
-#define                     MXVR_ALLOC_7  0xffc02758   /* MXVR Allocation Table Register 7 */
-#define                     MXVR_ALLOC_8  0xffc0275c   /* MXVR Allocation Table Register 8 */
-#define                     MXVR_ALLOC_9  0xffc02760   /* MXVR Allocation Table Register 9 */
-#define                    MXVR_ALLOC_10  0xffc02764   /* MXVR Allocation Table Register 10 */
-#define                    MXVR_ALLOC_11  0xffc02768   /* MXVR Allocation Table Register 11 */
-#define                    MXVR_ALLOC_12  0xffc0276c   /* MXVR Allocation Table Register 12 */
-#define                    MXVR_ALLOC_13  0xffc02770   /* MXVR Allocation Table Register 13 */
-#define                    MXVR_ALLOC_14  0xffc02774   /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define                MXVR_SYNC_LCHAN_0  0xffc02778   /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define                MXVR_SYNC_LCHAN_1  0xffc0277c   /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define                MXVR_SYNC_LCHAN_2  0xffc02780   /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define                MXVR_SYNC_LCHAN_3  0xffc02784   /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define                MXVR_SYNC_LCHAN_4  0xffc02788   /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define                MXVR_SYNC_LCHAN_5  0xffc0278c   /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define                MXVR_SYNC_LCHAN_6  0xffc02790   /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define                MXVR_SYNC_LCHAN_7  0xffc02794   /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define                 MXVR_DMA0_CONFIG  0xffc02798   /* MXVR Sync Data DMA0 Config Register */
-#define             MXVR_DMA0_START_ADDR  0xffc0279c   /* MXVR Sync Data DMA0 Start Address */
-#define                  MXVR_DMA0_COUNT  0xffc027a0   /* MXVR Sync Data DMA0 Loop Count Register */
-#define              MXVR_DMA0_CURR_ADDR  0xffc027a4   /* MXVR Sync Data DMA0 Current Address */
-#define             MXVR_DMA0_CURR_COUNT  0xffc027a8   /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define                 MXVR_DMA1_CONFIG  0xffc027ac   /* MXVR Sync Data DMA1 Config Register */
-#define             MXVR_DMA1_START_ADDR  0xffc027b0   /* MXVR Sync Data DMA1 Start Address */
-#define                  MXVR_DMA1_COUNT  0xffc027b4   /* MXVR Sync Data DMA1 Loop Count Register */
-#define              MXVR_DMA1_CURR_ADDR  0xffc027b8   /* MXVR Sync Data DMA1 Current Address */
-#define             MXVR_DMA1_CURR_COUNT  0xffc027bc   /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define                 MXVR_DMA2_CONFIG  0xffc027c0   /* MXVR Sync Data DMA2 Config Register */
-#define             MXVR_DMA2_START_ADDR  0xffc027c4   /* MXVR Sync Data DMA2 Start Address */
-#define                  MXVR_DMA2_COUNT  0xffc027c8   /* MXVR Sync Data DMA2 Loop Count Register */
-#define              MXVR_DMA2_CURR_ADDR  0xffc027cc   /* MXVR Sync Data DMA2 Current Address */
-#define             MXVR_DMA2_CURR_COUNT  0xffc027d0   /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define                 MXVR_DMA3_CONFIG  0xffc027d4   /* MXVR Sync Data DMA3 Config Register */
-#define             MXVR_DMA3_START_ADDR  0xffc027d8   /* MXVR Sync Data DMA3 Start Address */
-#define                  MXVR_DMA3_COUNT  0xffc027dc   /* MXVR Sync Data DMA3 Loop Count Register */
-#define              MXVR_DMA3_CURR_ADDR  0xffc027e0   /* MXVR Sync Data DMA3 Current Address */
-#define             MXVR_DMA3_CURR_COUNT  0xffc027e4   /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define                 MXVR_DMA4_CONFIG  0xffc027e8   /* MXVR Sync Data DMA4 Config Register */
-#define             MXVR_DMA4_START_ADDR  0xffc027ec   /* MXVR Sync Data DMA4 Start Address */
-#define                  MXVR_DMA4_COUNT  0xffc027f0   /* MXVR Sync Data DMA4 Loop Count Register */
-#define              MXVR_DMA4_CURR_ADDR  0xffc027f4   /* MXVR Sync Data DMA4 Current Address */
-#define             MXVR_DMA4_CURR_COUNT  0xffc027f8   /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define                 MXVR_DMA5_CONFIG  0xffc027fc   /* MXVR Sync Data DMA5 Config Register */
-#define             MXVR_DMA5_START_ADDR  0xffc02800   /* MXVR Sync Data DMA5 Start Address */
-#define                  MXVR_DMA5_COUNT  0xffc02804   /* MXVR Sync Data DMA5 Loop Count Register */
-#define              MXVR_DMA5_CURR_ADDR  0xffc02808   /* MXVR Sync Data DMA5 Current Address */
-#define             MXVR_DMA5_CURR_COUNT  0xffc0280c   /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define                 MXVR_DMA6_CONFIG  0xffc02810   /* MXVR Sync Data DMA6 Config Register */
-#define             MXVR_DMA6_START_ADDR  0xffc02814   /* MXVR Sync Data DMA6 Start Address */
-#define                  MXVR_DMA6_COUNT  0xffc02818   /* MXVR Sync Data DMA6 Loop Count Register */
-#define              MXVR_DMA6_CURR_ADDR  0xffc0281c   /* MXVR Sync Data DMA6 Current Address */
-#define             MXVR_DMA6_CURR_COUNT  0xffc02820   /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define                 MXVR_DMA7_CONFIG  0xffc02824   /* MXVR Sync Data DMA7 Config Register */
-#define             MXVR_DMA7_START_ADDR  0xffc02828   /* MXVR Sync Data DMA7 Start Address */
-#define                  MXVR_DMA7_COUNT  0xffc0282c   /* MXVR Sync Data DMA7 Loop Count Register */
-#define              MXVR_DMA7_CURR_ADDR  0xffc02830   /* MXVR Sync Data DMA7 Current Address */
-#define             MXVR_DMA7_CURR_COUNT  0xffc02834   /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define                      MXVR_AP_CTL  0xffc02838   /* MXVR Async Packet Control Register */
-#define             MXVR_APRB_START_ADDR  0xffc0283c   /* MXVR Async Packet RX Buffer Start Addr Register */
-#define              MXVR_APRB_CURR_ADDR  0xffc02840   /* MXVR Async Packet RX Buffer Current Addr Register */
-#define             MXVR_APTB_START_ADDR  0xffc02844   /* MXVR Async Packet TX Buffer Start Addr Register */
-#define              MXVR_APTB_CURR_ADDR  0xffc02848   /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define                      MXVR_CM_CTL  0xffc0284c   /* MXVR Control Message Control Register */
-#define             MXVR_CMRB_START_ADDR  0xffc02850   /* MXVR Control Message RX Buffer Start Addr Register */
-#define              MXVR_CMRB_CURR_ADDR  0xffc02854   /* MXVR Control Message RX Buffer Current Address */
-#define             MXVR_CMTB_START_ADDR  0xffc02858   /* MXVR Control Message TX Buffer Start Addr Register */
-#define              MXVR_CMTB_CURR_ADDR  0xffc0285c   /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define             MXVR_RRDB_START_ADDR  0xffc02860   /* MXVR Remote Read Buffer Start Addr Register */
-#define              MXVR_RRDB_CURR_ADDR  0xffc02864   /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define                  MXVR_PAT_DATA_0  0xffc02868   /* MXVR Pattern Data Register 0 */
-#define                    MXVR_PAT_EN_0  0xffc0286c   /* MXVR Pattern Enable Register 0 */
-#define                  MXVR_PAT_DATA_1  0xffc02870   /* MXVR Pattern Data Register 1 */
-#define                    MXVR_PAT_EN_1  0xffc02874   /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define                 MXVR_FRAME_CNT_0  0xffc02878   /* MXVR Frame Counter 0 */
-#define                 MXVR_FRAME_CNT_1  0xffc0287c   /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define                   MXVR_ROUTING_0  0xffc02880   /* MXVR Routing Table Register 0 */
-#define                   MXVR_ROUTING_1  0xffc02884   /* MXVR Routing Table Register 1 */
-#define                   MXVR_ROUTING_2  0xffc02888   /* MXVR Routing Table Register 2 */
-#define                   MXVR_ROUTING_3  0xffc0288c   /* MXVR Routing Table Register 3 */
-#define                   MXVR_ROUTING_4  0xffc02890   /* MXVR Routing Table Register 4 */
-#define                   MXVR_ROUTING_5  0xffc02894   /* MXVR Routing Table Register 5 */
-#define                   MXVR_ROUTING_6  0xffc02898   /* MXVR Routing Table Register 6 */
-#define                   MXVR_ROUTING_7  0xffc0289c   /* MXVR Routing Table Register 7 */
-#define                   MXVR_ROUTING_8  0xffc028a0   /* MXVR Routing Table Register 8 */
-#define                   MXVR_ROUTING_9  0xffc028a4   /* MXVR Routing Table Register 9 */
-#define                  MXVR_ROUTING_10  0xffc028a8   /* MXVR Routing Table Register 10 */
-#define                  MXVR_ROUTING_11  0xffc028ac   /* MXVR Routing Table Register 11 */
-#define                  MXVR_ROUTING_12  0xffc028b0   /* MXVR Routing Table Register 12 */
-#define                  MXVR_ROUTING_13  0xffc028b4   /* MXVR Routing Table Register 13 */
-#define                  MXVR_ROUTING_14  0xffc028b8   /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define                   MXVR_BLOCK_CNT  0xffc028c0   /* MXVR Block Counter */
-#define                     MXVR_CLK_CTL  0xffc028d0   /* MXVR Clock Control Register */
-#define                  MXVR_CDRPLL_CTL  0xffc028d4   /* MXVR Clock/Data Recovery PLL Control Register */
-#define                   MXVR_FMPLL_CTL  0xffc028d8   /* MXVR Frequency Multiply PLL Control Register */
-#define                     MXVR_PIN_CTL  0xffc028dc   /* MXVR Pin Control Register */
-#define                    MXVR_SCLK_CNT  0xffc028e0   /* MXVR System Clock Counter Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOSTDP Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOSTDP Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOSTDP Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                 HOSTDP_EN  0x1        /* HOSTDP Enable */
-#define                nHOSTDP_EN  0x0
-#define                HOSTDP_END  0x2        /* Host Endianess */
-#define               nHOSTDP_END  0x0
-#define          HOSTDP_DATA_SIZE  0x4        /* Data Size */
-#define         nHOSTDP_DATA_SIZE  0x0
-#define                HOSTDP_RST  0x8        /* HOSTDP Reset */
-#define               nHOSTDP_RST  0x0
-#define                  HRDY_OVR  0x20       /* HRDY Override */
-#define                 nHRDY_OVR  0x0
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0
-#define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0
-#define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0
-#define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                   DMA_RDY  0x1        /* DMA Ready */
-#define                  nDMA_RDY  0x0
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0
-#define                 DMA_CMPLT  0x8        /* DMA Complete */
-#define                nDMA_CMPLT  0x0
-#define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0
-#define               HOSTDP_TOUT  0x20       /* HOSTDP Timeout */
-#define              nHOSTDP_TOUT  0x0
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* HOSTDP Timeout count */
-
-/* Bit masks for MXVR_CONFIG */
-
-#define                    MXVREN  0x1        /* MXVR Enable */
-#define                   nMXVREN  0x0
-#define                      MMSM  0x2        /* MXVR Master/Slave Mode Select */
-#define                     nMMSM  0x0
-#define                    ACTIVE  0x4        /* Active Mode */
-#define                   nACTIVE  0x0
-#define                    SDELAY  0x8        /* Synchronous Data Delay */
-#define                   nSDELAY  0x0
-#define                   NCMRXEN  0x10       /* Normal Control Message Receive Enable */
-#define                  nNCMRXEN  0x0
-#define                   RWRRXEN  0x20       /* Remote Write Receive Enable */
-#define                  nRWRRXEN  0x0
-#define                     MTXEN  0x40       /* MXVR Transmit Data Enable */
-#define                    nMTXEN  0x0
-#define                    MTXONB  0x80       /* MXVR Phy Transmitter On */
-#define                   nMTXONB  0x0
-#define                   EPARITY  0x100      /* Even Parity Select */
-#define                  nEPARITY  0x0
-#define                       MSB  0x1e00     /* Master Synchronous Boundary */
-#define                    APRXEN  0x2000     /* Asynchronous Packet Receive Enable */
-#define                   nAPRXEN  0x0
-#define                    WAKEUP  0x4000     /* Wake-Up */
-#define                   nWAKEUP  0x0
-#define                     LMECH  0x8000     /* Lock Mechanism Select */
-#define                    nLMECH  0x0
-
-/* Bit masks for MXVR_STATE_0 */
-
-#define                      NACT  0x1        /* Network Activity */
-#define                     nNACT  0x0
-#define                    SBLOCK  0x2        /* Super Block Lock */
-#define                   nSBLOCK  0x0
-#define                   FMPLLST  0xc        /* Frequency Multiply PLL SM State */
-#define                  CDRPLLST  0xe0       /* Clock/Data Recovery PLL SM State */
-#define                     APBSY  0x100      /* Asynchronous Packet Transmit Buffer Busy */
-#define                    nAPBSY  0x0
-#define                     APARB  0x200      /* Asynchronous Packet Arbitrating */
-#define                    nAPARB  0x0
-#define                      APTX  0x400      /* Asynchronous Packet Transmitting */
-#define                     nAPTX  0x0
-#define                      APRX  0x800      /* Receiving Asynchronous Packet */
-#define                     nAPRX  0x0
-#define                     CMBSY  0x1000     /* Control Message Transmit Buffer Busy */
-#define                    nCMBSY  0x0
-#define                     CMARB  0x2000     /* Control Message Arbitrating */
-#define                    nCMARB  0x0
-#define                      CMTX  0x4000     /* Control Message Transmitting */
-#define                     nCMTX  0x0
-#define                      CMRX  0x8000     /* Receiving Control Message */
-#define                     nCMRX  0x0
-#define                    MRXONB  0x10000    /* MRXONB Pin State */
-#define                   nMRXONB  0x0
-#define                     RGSIP  0x20000    /* Remote Get Source In Progress */
-#define                    nRGSIP  0x0
-#define                     DALIP  0x40000    /* Resource Deallocate In Progress */
-#define                    nDALIP  0x0
-#define                      ALIP  0x80000    /* Resource Allocate In Progress */
-#define                     nALIP  0x0
-#define                     RRDIP  0x100000   /* Remote Read In Progress */
-#define                    nRRDIP  0x0
-#define                     RWRIP  0x200000   /* Remote Write In Progress */
-#define                    nRWRIP  0x0
-#define                     FLOCK  0x400000   /* Frame Lock */
-#define                    nFLOCK  0x0
-#define                     BLOCK  0x800000   /* Block Lock */
-#define                    nBLOCK  0x0
-#define                       RSB  0xf000000  /* Received Synchronous Boundary */
-#define                   DERRNUM  0xf0000000 /* DMA Error Channel Number */
-
-/* Bit masks for MXVR_STATE_1 */
-
-#define                   SRXNUMB  0xf        /* Synchronous Receive FIFO Number of Bytes */
-#define                   STXNUMB  0xf0       /* Synchronous Transmit FIFO Number of Bytes */
-#define                    APCONT  0x100      /* Asynchronous Packet Continuation */
-#define                   nAPCONT  0x0
-#define                  OBERRNUM  0xe00      /* DMA Out of Bounds Error Channel Number */
-#define                DMAACTIVE0  0x10000    /* DMA0 Active */
-#define               nDMAACTIVE0  0x0
-#define                DMAACTIVE1  0x20000    /* DMA1 Active */
-#define               nDMAACTIVE1  0x0
-#define                DMAACTIVE2  0x40000    /* DMA2 Active */
-#define               nDMAACTIVE2  0x0
-#define                DMAACTIVE3  0x80000    /* DMA3 Active */
-#define               nDMAACTIVE3  0x0
-#define                DMAACTIVE4  0x100000   /* DMA4 Active */
-#define               nDMAACTIVE4  0x0
-#define                DMAACTIVE5  0x200000   /* DMA5 Active */
-#define               nDMAACTIVE5  0x0
-#define                DMAACTIVE6  0x400000   /* DMA6 Active */
-#define               nDMAACTIVE6  0x0
-#define                DMAACTIVE7  0x800000   /* DMA7 Active */
-#define               nDMAACTIVE7  0x0
-#define                  DMAPMEN0  0x1000000  /* DMA0 Pattern Matching Enabled */
-#define                 nDMAPMEN0  0x0
-#define                  DMAPMEN1  0x2000000  /* DMA1 Pattern Matching Enabled */
-#define                 nDMAPMEN1  0x0
-#define                  DMAPMEN2  0x4000000  /* DMA2 Pattern Matching Enabled */
-#define                 nDMAPMEN2  0x0
-#define                  DMAPMEN3  0x8000000  /* DMA3 Pattern Matching Enabled */
-#define                 nDMAPMEN3  0x0
-#define                  DMAPMEN4  0x10000000 /* DMA4 Pattern Matching Enabled */
-#define                 nDMAPMEN4  0x0
-#define                  DMAPMEN5  0x20000000 /* DMA5 Pattern Matching Enabled */
-#define                 nDMAPMEN5  0x0
-#define                  DMAPMEN6  0x40000000 /* DMA6 Pattern Matching Enabled */
-#define                 nDMAPMEN6  0x0
-#define                  DMAPMEN7  0x80000000 /* DMA7 Pattern Matching Enabled */
-#define                 nDMAPMEN7  0x0
-
-/* Bit masks for MXVR_INT_STAT_0 */
-
-#define                      NI2A  0x1        /* Network Inactive to Active */
-#define                     nNI2A  0x0
-#define                      NA2I  0x2        /* Network Active to Inactive */
-#define                     nNA2I  0x0
-#define                     SBU2L  0x4        /* Super Block Unlock to Lock */
-#define                    nSBU2L  0x0
-#define                     SBL2U  0x8        /* Super Block Lock to Unlock */
-#define                    nSBL2U  0x0
-#define                       PRU  0x10       /* Position Register Updated */
-#define                      nPRU  0x0
-#define                      MPRU  0x20       /* Maximum Position Register Updated */
-#define                     nMPRU  0x0
-#define                       DRU  0x40       /* Delay Register Updated */
-#define                      nDRU  0x0
-#define                      MDRU  0x80       /* Maximum Delay Register Updated */
-#define                     nMDRU  0x0
-#define                       SBU  0x100      /* Synchronous Boundary Updated */
-#define                      nSBU  0x0
-#define                       ATU  0x200      /* Allocation Table Updated */
-#define                      nATU  0x0
-#define                      FCZ0  0x400      /* Frame Counter 0 Zero */
-#define                     nFCZ0  0x0
-#define                      FCZ1  0x800      /* Frame Counter 1 Zero */
-#define                     nFCZ1  0x0
-#define                      PERR  0x1000     /* Parity Error */
-#define                     nPERR  0x0
-#define                      MH2L  0x2000     /* MRXONB High to Low */
-#define                     nMH2L  0x0
-#define                      ML2H  0x4000     /* MRXONB Low to High */
-#define                     nML2H  0x0
-#define                       WUP  0x8000     /* Wake-Up Preamble Received */
-#define                      nWUP  0x0
-#define                      FU2L  0x10000    /* Frame Unlock to Lock */
-#define                     nFU2L  0x0
-#define                      FL2U  0x20000    /* Frame Lock to Unlock */
-#define                     nFL2U  0x0
-#define                      BU2L  0x40000    /* Block Unlock to Lock */
-#define                     nBU2L  0x0
-#define                      BL2U  0x80000    /* Block Lock to Unlock */
-#define                     nBL2U  0x0
-#define                     OBERR  0x100000   /* DMA Out of Bounds Error */
-#define                    nOBERR  0x0
-#define                       PFL  0x200000   /* PLL Frequency Locked */
-#define                      nPFL  0x0
-#define                       SCZ  0x400000   /* System Clock Counter Zero */
-#define                      nSCZ  0x0
-#define                      FERR  0x800000   /* FIFO Error */
-#define                     nFERR  0x0
-#define                       CMR  0x1000000  /* Control Message Received */
-#define                      nCMR  0x0
-#define                     CMROF  0x2000000  /* Control Message Receive Buffer Overflow */
-#define                    nCMROF  0x0
-#define                      CMTS  0x4000000  /* Control Message Transmit Buffer Successfully Sent */
-#define                     nCMTS  0x0
-#define                      CMTC  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled */
-#define                     nCMTC  0x0
-#define                      RWRC  0x10000000 /* Remote Write Control Message Completed */
-#define                     nRWRC  0x0
-#define                       BCZ  0x20000000 /* Block Counter Zero */
-#define                      nBCZ  0x0
-#define                     BMERR  0x40000000 /* Biphase Mark Coding Error */
-#define                    nBMERR  0x0
-#define                      DERR  0x80000000 /* DMA Error */
-#define                     nDERR  0x0
-
-/* Bit masks for MXVR_INT_STAT_1 */
-
-#define                    HDONE0  0x1        /* DMA0 Half Done */
-#define                   nHDONE0  0x0
-#define                     DONE0  0x2        /* DMA0 Done */
-#define                    nDONE0  0x0
-#define                       APR  0x4        /* Asynchronous Packet Received */
-#define                      nAPR  0x0
-#define                     APROF  0x8        /* Asynchronous Packet Receive Buffer Overflow */
-#define                    nAPROF  0x0
-#define                    HDONE1  0x10       /* DMA1 Half Done */
-#define                   nHDONE1  0x0
-#define                     DONE1  0x20       /* DMA1 Done */
-#define                    nDONE1  0x0
-#define                      APTS  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent */
-#define                     nAPTS  0x0
-#define                      APTC  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
-#define                     nAPTC  0x0
-#define                    HDONE2  0x100      /* DMA2 Half Done */
-#define                   nHDONE2  0x0
-#define                     DONE2  0x200      /* DMA2 Done */
-#define                    nDONE2  0x0
-#define                     APRCE  0x400      /* Asynchronous Packet Receive CRC Error */
-#define                    nAPRCE  0x0
-#define                     APRPE  0x800      /* Asynchronous Packet Receive Packet Error */
-#define                    nAPRPE  0x0
-#define                    HDONE3  0x1000     /* DMA3 Half Done */
-#define                   nHDONE3  0x0
-#define                     DONE3  0x2000     /* DMA3 Done */
-#define                    nDONE3  0x0
-#define                    HDONE4  0x10000    /* DMA4 Half Done */
-#define                   nHDONE4  0x0
-#define                     DONE4  0x20000    /* DMA4 Done */
-#define                    nDONE4  0x0
-#define                    HDONE5  0x100000   /* DMA5 Half Done */
-#define                   nHDONE5  0x0
-#define                     DONE5  0x200000   /* DMA5 Done */
-#define                    nDONE5  0x0
-#define                    HDONE6  0x1000000  /* DMA6 Half Done */
-#define                   nHDONE6  0x0
-#define                     DONE6  0x2000000  /* DMA6 Done */
-#define                    nDONE6  0x0
-#define                    HDONE7  0x10000000 /* DMA7 Half Done */
-#define                   nHDONE7  0x0
-#define                     DONE7  0x20000000 /* DMA7 Done */
-#define                    nDONE7  0x0
-
-/* Bit masks for MXVR_INT_EN_0 */
-
-#define                    NI2AEN  0x1        /* Network Inactive to Active Interrupt Enable */
-#define                   nNI2AEN  0x0
-#define                    NA2IEN  0x2        /* Network Active to Inactive Interrupt Enable */
-#define                   nNA2IEN  0x0
-#define                   SBU2LEN  0x4        /* Super Block Unlock to Lock Interrupt Enable */
-#define                  nSBU2LEN  0x0
-#define                   SBL2UEN  0x8        /* Super Block Lock to Unlock Interrupt Enable */
-#define                  nSBL2UEN  0x0
-#define                     PRUEN  0x10       /* Position Register Updated Interrupt Enable */
-#define                    nPRUEN  0x0
-#define                    MPRUEN  0x20       /* Maximum Position Register Updated Interrupt Enable */
-#define                   nMPRUEN  0x0
-#define                     DRUEN  0x40       /* Delay Register Updated Interrupt Enable */
-#define                    nDRUEN  0x0
-#define                    MDRUEN  0x80       /* Maximum Delay Register Updated Interrupt Enable */
-#define                   nMDRUEN  0x0
-#define                     SBUEN  0x100      /* Synchronous Boundary Updated Interrupt Enable */
-#define                    nSBUEN  0x0
-#define                     ATUEN  0x200      /* Allocation Table Updated Interrupt Enable */
-#define                    nATUEN  0x0
-#define                    FCZ0EN  0x400      /* Frame Counter 0 Zero Interrupt Enable */
-#define                   nFCZ0EN  0x0
-#define                    FCZ1EN  0x800      /* Frame Counter 1 Zero Interrupt Enable */
-#define                   nFCZ1EN  0x0
-#define                    PERREN  0x1000     /* Parity Error Interrupt Enable */
-#define                   nPERREN  0x0
-#define                    MH2LEN  0x2000     /* MRXONB High to Low Interrupt Enable */
-#define                   nMH2LEN  0x0
-#define                    ML2HEN  0x4000     /* MRXONB Low to High Interrupt Enable */
-#define                   nML2HEN  0x0
-#define                     WUPEN  0x8000     /* Wake-Up Preamble Received Interrupt Enable */
-#define                    nWUPEN  0x0
-#define                    FU2LEN  0x10000    /* Frame Unlock to Lock Interrupt Enable */
-#define                   nFU2LEN  0x0
-#define                    FL2UEN  0x20000    /* Frame Lock to Unlock Interrupt Enable */
-#define                   nFL2UEN  0x0
-#define                    BU2LEN  0x40000    /* Block Unlock to Lock Interrupt Enable */
-#define                   nBU2LEN  0x0
-#define                    BL2UEN  0x80000    /* Block Lock to Unlock Interrupt Enable */
-#define                   nBL2UEN  0x0
-#define                   OBERREN  0x100000   /* DMA Out of Bounds Error Interrupt Enable */
-#define                  nOBERREN  0x0
-#define                     PFLEN  0x200000   /* PLL Frequency Locked Interrupt Enable */
-#define                    nPFLEN  0x0
-#define                     SCZEN  0x400000   /* System Clock Counter Zero Interrupt Enable */
-#define                    nSCZEN  0x0
-#define                    FERREN  0x800000   /* FIFO Error Interrupt Enable */
-#define                   nFERREN  0x0
-#define                     CMREN  0x1000000  /* Control Message Received Interrupt Enable */
-#define                    nCMREN  0x0
-#define                   CMROFEN  0x2000000  /* Control Message Receive Buffer Overflow Interrupt Enable */
-#define                  nCMROFEN  0x0
-#define                    CMTSEN  0x4000000  /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
-#define                   nCMTSEN  0x0
-#define                    CMTCEN  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                   nCMTCEN  0x0
-#define                    RWRCEN  0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
-#define                   nRWRCEN  0x0
-#define                     BCZEN  0x20000000 /* Block Counter Zero Interrupt Enable */
-#define                    nBCZEN  0x0
-#define                   BMERREN  0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
-#define                  nBMERREN  0x0
-#define                    DERREN  0x80000000 /* DMA Error Interrupt Enable */
-#define                   nDERREN  0x0
-
-/* Bit masks for MXVR_INT_EN_1 */
-
-#define                  HDONEEN0  0x1        /* DMA0 Half Done Interrupt Enable */
-#define                 nHDONEEN0  0x0
-#define                   DONEEN0  0x2        /* DMA0 Done Interrupt Enable */
-#define                  nDONEEN0  0x0
-#define                     APREN  0x4        /* Asynchronous Packet Received Interrupt Enable */
-#define                    nAPREN  0x0
-#define                   APROFEN  0x8        /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
-#define                  nAPROFEN  0x0
-#define                  HDONEEN1  0x10       /* DMA1 Half Done Interrupt Enable */
-#define                 nHDONEEN1  0x0
-#define                   DONEEN1  0x20       /* DMA1 Done Interrupt Enable */
-#define                  nDONEEN1  0x0
-#define                    APTSEN  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
-#define                   nAPTSEN  0x0
-#define                    APTCEN  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                   nAPTCEN  0x0
-#define                  HDONEEN2  0x100      /* DMA2 Half Done Interrupt Enable */
-#define                 nHDONEEN2  0x0
-#define                   DONEEN2  0x200      /* DMA2 Done Interrupt Enable */
-#define                  nDONEEN2  0x0
-#define                   APRCEEN  0x400      /* Asynchronous Packet Receive CRC Error Interrupt Enable */
-#define                  nAPRCEEN  0x0
-#define                   APRPEEN  0x800      /* Asynchronous Packet Receive Packet Error Interrupt Enable */
-#define                  nAPRPEEN  0x0
-#define                  HDONEEN3  0x1000     /* DMA3 Half Done Interrupt Enable */
-#define                 nHDONEEN3  0x0
-#define                   DONEEN3  0x2000     /* DMA3 Done Interrupt Enable */
-#define                  nDONEEN3  0x0
-#define                  HDONEEN4  0x10000    /* DMA4 Half Done Interrupt Enable */
-#define                 nHDONEEN4  0x0
-#define                   DONEEN4  0x20000    /* DMA4 Done Interrupt Enable */
-#define                  nDONEEN4  0x0
-#define                  HDONEEN5  0x100000   /* DMA5 Half Done Interrupt Enable */
-#define                 nHDONEEN5  0x0
-#define                   DONEEN5  0x200000   /* DMA5 Done Interrupt Enable */
-#define                  nDONEEN5  0x0
-#define                  HDONEEN6  0x1000000  /* DMA6 Half Done Interrupt Enable */
-#define                 nHDONEEN6  0x0
-#define                   DONEEN6  0x2000000  /* DMA6 Done Interrupt Enable */
-#define                  nDONEEN6  0x0
-#define                  HDONEEN7  0x10000000 /* DMA7 Half Done Interrupt Enable */
-#define                 nHDONEEN7  0x0
-#define                   DONEEN7  0x20000000 /* DMA7 Done Interrupt Enable */
-#define                  nDONEEN7  0x0
-
-/* Bit masks for MXVR_POSITION */
-
-#define                  POSITION  0x3f       /* Node Position */
-#define                    PVALID  0x8000     /* Node Position Valid */
-#define                   nPVALID  0x0
-
-/* Bit masks for MXVR_MAX_POSITION */
-
-#define                 MPOSITION  0x3f       /* Maximum Node Position */
-#define                   MPVALID  0x8000     /* Maximum Node Position Valid */
-#define                  nMPVALID  0x0
-
-/* Bit masks for MXVR_DELAY */
-
-#define                     DELAY  0x3f       /* Node Frame Delay */
-#define                    DVALID  0x8000     /* Node Frame Delay Valid */
-#define                   nDVALID  0x0
-
-/* Bit masks for MXVR_MAX_DELAY */
-
-#define                    MDELAY  0x3f       /* Maximum Node Frame Delay */
-#define                   MDVALID  0x8000     /* Maximum Node Frame Delay Valid */
-#define                  nMDVALID  0x0
-
-/* Bit masks for MXVR_LADDR */
-
-#define                     LADDR  0xffff     /* Logical Address */
-#define                    LVALID  0x80000000 /* Logical Address Valid */
-#define                   nLVALID  0x0
-
-/* Bit masks for MXVR_GADDR */
-
-#define                    GADDRL  0xff       /* Group Address Lower Byte */
-#define                    GVALID  0x8000     /* Group Address Valid */
-#define                   nGVALID  0x0
-
-/* Bit masks for MXVR_AADDR */
-
-#define                     AADDR  0xffff     /* Alternate Address */
-#define                    AVALID  0x80000000 /* Alternate Address Valid */
-#define                   nAVALID  0x0
-
-/* Bit masks for MXVR_ALLOC_0 */
-
-#define                       CL0  0x7f       /* Channel 0 Connection Label */
-#define                      CIU0  0x80       /* Channel 0 In Use */
-#define                     nCIU0  0x0
-#define                       CL1  0x7f00     /* Channel 0 Connection Label */
-#define                      CIU1  0x8000     /* Channel 0 In Use */
-#define                     nCIU1  0x0
-#define                       CL2  0x7f0000   /* Channel 0 Connection Label */
-#define                      CIU2  0x800000   /* Channel 0 In Use */
-#define                     nCIU2  0x0
-#define                       CL3  0x7f000000 /* Channel 0 Connection Label */
-#define                      CIU3  0x80000000 /* Channel 0 In Use */
-#define                     nCIU3  0x0
-
-/* Bit masks for MXVR_ALLOC_1 */
-
-#define                       CL4  0x7f       /* Channel 4 Connection Label */
-#define                      CIU4  0x80       /* Channel 4 In Use */
-#define                     nCIU4  0x0
-#define                       CL5  0x7f00     /* Channel 5 Connection Label */
-#define                      CIU5  0x8000     /* Channel 5 In Use */
-#define                     nCIU5  0x0
-#define                       CL6  0x7f0000   /* Channel 6 Connection Label */
-#define                      CIU6  0x800000   /* Channel 6 In Use */
-#define                     nCIU6  0x0
-#define                       CL7  0x7f000000 /* Channel 7 Connection Label */
-#define                      CIU7  0x80000000 /* Channel 7 In Use */
-#define                     nCIU7  0x0
-
-/* Bit masks for MXVR_ALLOC_2 */
-
-#define                       CL8  0x7f       /* Channel 8 Connection Label */
-#define                      CIU8  0x80       /* Channel 8 In Use */
-#define                     nCIU8  0x0
-#define                       CL9  0x7f00     /* Channel 9 Connection Label */
-#define                      CIU9  0x8000     /* Channel 9 In Use */
-#define                     nCIU9  0x0
-#define                      CL10  0x7f0000   /* Channel 10 Connection Label */
-#define                     CIU10  0x800000   /* Channel 10 In Use */
-#define                    nCIU10  0x0
-#define                      CL11  0x7f000000 /* Channel 11 Connection Label */
-#define                     CIU11  0x80000000 /* Channel 11 In Use */
-#define                    nCIU11  0x0
-
-/* Bit masks for MXVR_ALLOC_3 */
-
-#define                      CL12  0x7f       /* Channel 12 Connection Label */
-#define                     CIU12  0x80       /* Channel 12 In Use */
-#define                    nCIU12  0x0
-#define                      CL13  0x7f00     /* Channel 13 Connection Label */
-#define                     CIU13  0x8000     /* Channel 13 In Use */
-#define                    nCIU13  0x0
-#define                      CL14  0x7f0000   /* Channel 14 Connection Label */
-#define                     CIU14  0x800000   /* Channel 14 In Use */
-#define                    nCIU14  0x0
-#define                      CL15  0x7f000000 /* Channel 15 Connection Label */
-#define                     CIU15  0x80000000 /* Channel 15 In Use */
-#define                    nCIU15  0x0
-
-/* Bit masks for MXVR_ALLOC_4 */
-
-#define                      CL16  0x7f       /* Channel 16 Connection Label */
-#define                     CIU16  0x80       /* Channel 16 In Use */
-#define                    nCIU16  0x0
-#define                      CL17  0x7f00     /* Channel 17 Connection Label */
-#define                     CIU17  0x8000     /* Channel 17 In Use */
-#define                    nCIU17  0x0
-#define                      CL18  0x7f0000   /* Channel 18 Connection Label */
-#define                     CIU18  0x800000   /* Channel 18 In Use */
-#define                    nCIU18  0x0
-#define                      CL19  0x7f000000 /* Channel 19 Connection Label */
-#define                     CIU19  0x80000000 /* Channel 19 In Use */
-#define                    nCIU19  0x0
-
-/* Bit masks for MXVR_ALLOC_5 */
-
-#define                      CL20  0x7f       /* Channel 20 Connection Label */
-#define                     CIU20  0x80       /* Channel 20 In Use */
-#define                    nCIU20  0x0
-#define                      CL21  0x7f00     /* Channel 21 Connection Label */
-#define                     CIU21  0x8000     /* Channel 21 In Use */
-#define                    nCIU21  0x0
-#define                      CL22  0x7f0000   /* Channel 22 Connection Label */
-#define                     CIU22  0x800000   /* Channel 22 In Use */
-#define                    nCIU22  0x0
-#define                      CL23  0x7f000000 /* Channel 23 Connection Label */
-#define                     CIU23  0x80000000 /* Channel 23 In Use */
-#define                    nCIU23  0x0
-
-/* Bit masks for MXVR_ALLOC_6 */
-
-#define                      CL24  0x7f       /* Channel 24 Connection Label */
-#define                     CIU24  0x80       /* Channel 24 In Use */
-#define                    nCIU24  0x0
-#define                      CL25  0x7f00     /* Channel 25 Connection Label */
-#define                     CIU25  0x8000     /* Channel 25 In Use */
-#define                    nCIU25  0x0
-#define                      CL26  0x7f0000   /* Channel 26 Connection Label */
-#define                     CIU26  0x800000   /* Channel 26 In Use */
-#define                    nCIU26  0x0
-#define                      CL27  0x7f000000 /* Channel 27 Connection Label */
-#define                     CIU27  0x80000000 /* Channel 27 In Use */
-#define                    nCIU27  0x0
-
-/* Bit masks for MXVR_ALLOC_7 */
-
-#define                      CL28  0x7f       /* Channel 28 Connection Label */
-#define                     CIU28  0x80       /* Channel 28 In Use */
-#define                    nCIU28  0x0
-#define                      CL29  0x7f00     /* Channel 29 Connection Label */
-#define                     CIU29  0x8000     /* Channel 29 In Use */
-#define                    nCIU29  0x0
-#define                      CL30  0x7f0000   /* Channel 30 Connection Label */
-#define                     CIU30  0x800000   /* Channel 30 In Use */
-#define                    nCIU30  0x0
-#define                      CL31  0x7f000000 /* Channel 31 Connection Label */
-#define                     CIU31  0x80000000 /* Channel 31 In Use */
-#define                    nCIU31  0x0
-
-/* Bit masks for MXVR_ALLOC_8 */
-
-#define                      CL32  0x7f       /* Channel 32 Connection Label */
-#define                     CIU32  0x80       /* Channel 32 In Use */
-#define                    nCIU32  0x0
-#define                      CL33  0x7f00     /* Channel 33 Connection Label */
-#define                     CIU33  0x8000     /* Channel 33 In Use */
-#define                    nCIU33  0x0
-#define                      CL34  0x7f0000   /* Channel 34 Connection Label */
-#define                     CIU34  0x800000   /* Channel 34 In Use */
-#define                    nCIU34  0x0
-#define                      CL35  0x7f000000 /* Channel 35 Connection Label */
-#define                     CIU35  0x80000000 /* Channel 35 In Use */
-#define                    nCIU35  0x0
-
-/* Bit masks for MXVR_ALLOC_9 */
-
-#define                      CL36  0x7f       /* Channel 36 Connection Label */
-#define                     CIU36  0x80       /* Channel 36 In Use */
-#define                    nCIU36  0x0
-#define                      CL37  0x7f00     /* Channel 37 Connection Label */
-#define                     CIU37  0x8000     /* Channel 37 In Use */
-#define                    nCIU37  0x0
-#define                      CL38  0x7f0000   /* Channel 38 Connection Label */
-#define                     CIU38  0x800000   /* Channel 38 In Use */
-#define                    nCIU38  0x0
-#define                      CL39  0x7f000000 /* Channel 39 Connection Label */
-#define                     CIU39  0x80000000 /* Channel 39 In Use */
-#define                    nCIU39  0x0
-
-/* Bit masks for MXVR_ALLOC_10 */
-
-#define                      CL40  0x7f       /* Channel 40 Connection Label */
-#define                     CIU40  0x80       /* Channel 40 In Use */
-#define                    nCIU40  0x0
-#define                      CL41  0x7f00     /* Channel 41 Connection Label */
-#define                     CIU41  0x8000     /* Channel 41 In Use */
-#define                    nCIU41  0x0
-#define                      CL42  0x7f0000   /* Channel 42 Connection Label */
-#define                     CIU42  0x800000   /* Channel 42 In Use */
-#define                    nCIU42  0x0
-#define                      CL43  0x7f000000 /* Channel 43 Connection Label */
-#define                     CIU43  0x80000000 /* Channel 43 In Use */
-#define                    nCIU43  0x0
-
-/* Bit masks for MXVR_ALLOC_11 */
-
-#define                      CL44  0x7f       /* Channel 44 Connection Label */
-#define                     CIU44  0x80       /* Channel 44 In Use */
-#define                    nCIU44  0x0
-#define                      CL45  0x7f00     /* Channel 45 Connection Label */
-#define                     CIU45  0x8000     /* Channel 45 In Use */
-#define                    nCIU45  0x0
-#define                      CL46  0x7f0000   /* Channel 46 Connection Label */
-#define                     CIU46  0x800000   /* Channel 46 In Use */
-#define                    nCIU46  0x0
-#define                      CL47  0x7f000000 /* Channel 47 Connection Label */
-#define                     CIU47  0x80000000 /* Channel 47 In Use */
-#define                    nCIU47  0x0
-
-/* Bit masks for MXVR_ALLOC_12 */
-
-#define                      CL48  0x7f       /* Channel 48 Connection Label */
-#define                     CIU48  0x80       /* Channel 48 In Use */
-#define                    nCIU48  0x0
-#define                      CL49  0x7f00     /* Channel 49 Connection Label */
-#define                     CIU49  0x8000     /* Channel 49 In Use */
-#define                    nCIU49  0x0
-#define                      CL50  0x7f0000   /* Channel 50 Connection Label */
-#define                     CIU50  0x800000   /* Channel 50 In Use */
-#define                    nCIU50  0x0
-#define                      CL51  0x7f000000 /* Channel 51 Connection Label */
-#define                     CIU51  0x80000000 /* Channel 51 In Use */
-#define                    nCIU51  0x0
-
-/* Bit masks for MXVR_ALLOC_13 */
-
-#define                      CL52  0x7f       /* Channel 52 Connection Label */
-#define                     CIU52  0x80       /* Channel 52 In Use */
-#define                    nCIU52  0x0
-#define                      CL53  0x7f00     /* Channel 53 Connection Label */
-#define                     CIU53  0x8000     /* Channel 53 In Use */
-#define                    nCIU53  0x0
-#define                      CL54  0x7f0000   /* Channel 54 Connection Label */
-#define                     CIU54  0x800000   /* Channel 54 In Use */
-#define                    nCIU54  0x0
-#define                      CL55  0x7f000000 /* Channel 55 Connection Label */
-#define                     CIU55  0x80000000 /* Channel 55 In Use */
-#define                    nCIU55  0x0
-
-/* Bit masks for MXVR_ALLOC_14 */
-
-#define                      CL56  0x7f       /* Channel 56 Connection Label */
-#define                     CIU56  0x80       /* Channel 56 In Use */
-#define                    nCIU56  0x0
-#define                      CL57  0x7f00     /* Channel 57 Connection Label */
-#define                     CIU57  0x8000     /* Channel 57 In Use */
-#define                    nCIU57  0x0
-#define                      CL58  0x7f0000   /* Channel 58 Connection Label */
-#define                     CIU58  0x800000   /* Channel 58 In Use */
-#define                    nCIU58  0x0
-#define                      CL59  0x7f000000 /* Channel 59 Connection Label */
-#define                     CIU59  0x80000000 /* Channel 59 In Use */
-#define                    nCIU59  0x0
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-/* Bit masks for MXVR_DMAx_CONFIG */
-
-#define                    MDMAEN  0x1        /* DMA Channel Enable */
-#define                   nMDMAEN  0x0
-#define                        DD  0x2        /* DMA Channel Direction */
-#define                       nDD  0x0
-#define                 BY4SWAPEN  0x20       /* DMA Channel Four Byte Swap Enable */
-#define                nBY4SWAPEN  0x0
-#define                     LCHAN  0x3c0      /* DMA Channel Logical Channel */
-#define                 BITSWAPEN  0x400      /* DMA Channel Bit Swap Enable */
-#define                nBITSWAPEN  0x0
-#define                 BY2SWAPEN  0x800      /* DMA Channel Two Byte Swap Enable */
-#define                nBY2SWAPEN  0x0
-#define                     MFLOW  0x7000     /* DMA Channel Operation Flow */
-#define                   FIXEDPM  0x80000    /* DMA Channel Fixed Pattern Matching Select */
-#define                  nFIXEDPM  0x0
-#define                  STARTPAT  0x300000   /* DMA Channel Start Pattern Select */
-#define                   STOPPAT  0xc00000   /* DMA Channel Stop Pattern Select */
-#define                  COUNTPOS  0x1c000000 /* DMA Channel Count Position */
-
-/* Bit masks for MXVR_AP_CTL */
-
-#define                   STARTAP  0x1        /* Start Asynchronous Packet Transmission */
-#define                  nSTARTAP  0x0
-#define                  CANCELAP  0x2        /* Cancel Asynchronous Packet Transmission */
-#define                 nCANCELAP  0x0
-#define                   RESETAP  0x4        /* Reset Asynchronous Packet Arbitration */
-#define                  nRESETAP  0x0
-#define                    APRBE0  0x4000     /* Asynchronous Packet Receive Buffer Entry 0 */
-#define                   nAPRBE0  0x0
-#define                    APRBE1  0x8000     /* Asynchronous Packet Receive Buffer Entry 1 */
-#define                   nAPRBE1  0x0
-
-/* Bit masks for MXVR_APRB_START_ADDR */
-
-#define           APRB_START_ADDR  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
-
-/* Bit masks for MXVR_APRB_CURR_ADDR */
-
-#define            APRB_CURR_ADDR  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
-
-/* Bit masks for MXVR_APTB_START_ADDR */
-
-#define           APTB_START_ADDR  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_APTB_CURR_ADDR */
-
-#define            APTB_CURR_ADDR  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_CM_CTL */
-
-#define                   STARTCM  0x1        /* Start Control Message Transmission */
-#define                  nSTARTCM  0x0
-#define                  CANCELCM  0x2        /* Cancel Control Message Transmission */
-#define                 nCANCELCM  0x0
-#define                    CMRBE0  0x10000    /* Control Message Receive Buffer Entry 0 */
-#define                   nCMRBE0  0x0
-#define                    CMRBE1  0x20000    /* Control Message Receive Buffer Entry 1 */
-#define                   nCMRBE1  0x0
-#define                    CMRBE2  0x40000    /* Control Message Receive Buffer Entry 2 */
-#define                   nCMRBE2  0x0
-#define                    CMRBE3  0x80000    /* Control Message Receive Buffer Entry 3 */
-#define                   nCMRBE3  0x0
-#define                    CMRBE4  0x100000   /* Control Message Receive Buffer Entry 4 */
-#define                   nCMRBE4  0x0
-#define                    CMRBE5  0x200000   /* Control Message Receive Buffer Entry 5 */
-#define                   nCMRBE5  0x0
-#define                    CMRBE6  0x400000   /* Control Message Receive Buffer Entry 6 */
-#define                   nCMRBE6  0x0
-#define                    CMRBE7  0x800000   /* Control Message Receive Buffer Entry 7 */
-#define                   nCMRBE7  0x0
-#define                    CMRBE8  0x1000000  /* Control Message Receive Buffer Entry 8 */
-#define                   nCMRBE8  0x0
-#define                    CMRBE9  0x2000000  /* Control Message Receive Buffer Entry 9 */
-#define                   nCMRBE9  0x0
-#define                   CMRBE10  0x4000000  /* Control Message Receive Buffer Entry 10 */
-#define                  nCMRBE10  0x0
-#define                   CMRBE11  0x8000000  /* Control Message Receive Buffer Entry 11 */
-#define                  nCMRBE11  0x0
-#define                   CMRBE12  0x10000000 /* Control Message Receive Buffer Entry 12 */
-#define                  nCMRBE12  0x0
-#define                   CMRBE13  0x20000000 /* Control Message Receive Buffer Entry 13 */
-#define                  nCMRBE13  0x0
-#define                   CMRBE14  0x40000000 /* Control Message Receive Buffer Entry 14 */
-#define                  nCMRBE14  0x0
-#define                   CMRBE15  0x80000000 /* Control Message Receive Buffer Entry 15 */
-#define                  nCMRBE15  0x0
-
-/* Bit masks for MXVR_CMRB_START_ADDR */
-
-#define           CMRB_START_ADDR  0x1fffffe  /* Control Message Receive Buffer Start Address */
-
-/* Bit masks for MXVR_CMRB_CURR_ADDR */
-
-#define            CMRB_CURR_ADDR  0xffffffff /* Control Message Receive Buffer Current Address */
-
-/* Bit masks for MXVR_CMTB_START_ADDR */
-
-#define           CMTB_START_ADDR  0x1fffffe  /* Control Message Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_CMTB_CURR_ADDR */
-
-#define            CMTB_CURR_ADDR  0xffffffff /* Control Message Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_RRDB_START_ADDR */
-
-#define           RRDB_START_ADDR  0x1fffffe  /* Remote Read Buffer Start Address */
-
-/* Bit masks for MXVR_RRDB_CURR_ADDR */
-
-#define            RRDB_CURR_ADDR  0xffffffff /* Remote Read Buffer Current Address */
-
-/* Bit masks for MXVR_PAT_DATAx */
-
-#define              MATCH_DATA_0  0xff       /* Pattern Match Data Byte 0 */
-#define              MATCH_DATA_1  0xff00     /* Pattern Match Data Byte 1 */
-#define              MATCH_DATA_2  0xff0000   /* Pattern Match Data Byte 2 */
-#define              MATCH_DATA_3  0xff000000 /* Pattern Match Data Byte 3 */
-
-/* Bit masks for MXVR_PAT_EN_0 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define             nMATCH_EN_0_0  0x0
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define             nMATCH_EN_0_1  0x0
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define             nMATCH_EN_0_2  0x0
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define             nMATCH_EN_0_3  0x0
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define             nMATCH_EN_0_4  0x0
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define             nMATCH_EN_0_5  0x0
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define             nMATCH_EN_0_6  0x0
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define             nMATCH_EN_0_7  0x0
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define             nMATCH_EN_1_0  0x0
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define             nMATCH_EN_1_1  0x0
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define             nMATCH_EN_1_2  0x0
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define             nMATCH_EN_1_3  0x0
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define             nMATCH_EN_1_4  0x0
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define             nMATCH_EN_1_5  0x0
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define             nMATCH_EN_1_6  0x0
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define             nMATCH_EN_1_7  0x0
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define             nMATCH_EN_2_0  0x0
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define             nMATCH_EN_2_1  0x0
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define             nMATCH_EN_2_2  0x0
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define             nMATCH_EN_2_3  0x0
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define             nMATCH_EN_2_4  0x0
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define             nMATCH_EN_2_5  0x0
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define             nMATCH_EN_2_6  0x0
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define             nMATCH_EN_2_7  0x0
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define             nMATCH_EN_3_0  0x0
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define             nMATCH_EN_3_1  0x0
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define             nMATCH_EN_3_2  0x0
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define             nMATCH_EN_3_3  0x0
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define             nMATCH_EN_3_4  0x0
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define             nMATCH_EN_3_5  0x0
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define             nMATCH_EN_3_6  0x0
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define             nMATCH_EN_3_7  0x0
-
-/* Bit masks for MXVR_PAT_EN_1 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define             nMATCH_EN_0_0  0x0
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define             nMATCH_EN_0_1  0x0
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define             nMATCH_EN_0_2  0x0
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define             nMATCH_EN_0_3  0x0
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define             nMATCH_EN_0_4  0x0
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define             nMATCH_EN_0_5  0x0
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define             nMATCH_EN_0_6  0x0
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define             nMATCH_EN_0_7  0x0
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define             nMATCH_EN_1_0  0x0
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define             nMATCH_EN_1_1  0x0
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define             nMATCH_EN_1_2  0x0
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define             nMATCH_EN_1_3  0x0
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define             nMATCH_EN_1_4  0x0
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define             nMATCH_EN_1_5  0x0
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define             nMATCH_EN_1_6  0x0
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define             nMATCH_EN_1_7  0x0
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define             nMATCH_EN_2_0  0x0
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define             nMATCH_EN_2_1  0x0
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define             nMATCH_EN_2_2  0x0
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define             nMATCH_EN_2_3  0x0
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define             nMATCH_EN_2_4  0x0
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define             nMATCH_EN_2_5  0x0
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define             nMATCH_EN_2_6  0x0
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define             nMATCH_EN_2_7  0x0
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define             nMATCH_EN_3_0  0x0
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define             nMATCH_EN_3_1  0x0
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define             nMATCH_EN_3_2  0x0
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define             nMATCH_EN_3_3  0x0
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define             nMATCH_EN_3_4  0x0
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define             nMATCH_EN_3_5  0x0
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define             nMATCH_EN_3_6  0x0
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define             nMATCH_EN_3_7  0x0
-
-/* Bit masks for MXVR_FRAME_CNT_0 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_FRAME_CNT_1 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_ROUTING_0 */
-
-#define                    TX_CH0  0x3f       /* Transmit Channel 0 */
-#define                  MUTE_CH0  0x80       /* Mute Channel 0 */
-#define                 nMUTE_CH0  0x0
-#define                    TX_CH1  0x3f00     /* Transmit Channel 0 */
-#define                  MUTE_CH1  0x8000     /* Mute Channel 0 */
-#define                 nMUTE_CH1  0x0
-#define                    TX_CH2  0x3f0000   /* Transmit Channel 0 */
-#define                  MUTE_CH2  0x800000   /* Mute Channel 0 */
-#define                 nMUTE_CH2  0x0
-#define                    TX_CH3  0x3f000000 /* Transmit Channel 0 */
-#define                  MUTE_CH3  0x80000000 /* Mute Channel 0 */
-#define                 nMUTE_CH3  0x0
-
-/* Bit masks for MXVR_ROUTING_1 */
-
-#define                    TX_CH4  0x3f       /* Transmit Channel 4 */
-#define                  MUTE_CH4  0x80       /* Mute Channel 4 */
-#define                 nMUTE_CH4  0x0
-#define                    TX_CH5  0x3f00     /* Transmit Channel 5 */
-#define                  MUTE_CH5  0x8000     /* Mute Channel 5 */
-#define                 nMUTE_CH5  0x0
-#define                    TX_CH6  0x3f0000   /* Transmit Channel 6 */
-#define                  MUTE_CH6  0x800000   /* Mute Channel 6 */
-#define                 nMUTE_CH6  0x0
-#define                    TX_CH7  0x3f000000 /* Transmit Channel 7 */
-#define                  MUTE_CH7  0x80000000 /* Mute Channel 7 */
-#define                 nMUTE_CH7  0x0
-
-/* Bit masks for MXVR_ROUTING_2 */
-
-#define                    TX_CH8  0x3f       /* Transmit Channel 8 */
-#define                  MUTE_CH8  0x80       /* Mute Channel 8 */
-#define                 nMUTE_CH8  0x0
-#define                    TX_CH9  0x3f00     /* Transmit Channel 9 */
-#define                  MUTE_CH9  0x8000     /* Mute Channel 9 */
-#define                 nMUTE_CH9  0x0
-#define                   TX_CH10  0x3f0000   /* Transmit Channel 10 */
-#define                 MUTE_CH10  0x800000   /* Mute Channel 10 */
-#define                nMUTE_CH10  0x0
-#define                   TX_CH11  0x3f000000 /* Transmit Channel 11 */
-#define                 MUTE_CH11  0x80000000 /* Mute Channel 11 */
-#define                nMUTE_CH11  0x0
-
-/* Bit masks for MXVR_ROUTING_3 */
-
-#define                   TX_CH12  0x3f       /* Transmit Channel 12 */
-#define                 MUTE_CH12  0x80       /* Mute Channel 12 */
-#define                nMUTE_CH12  0x0
-#define                   TX_CH13  0x3f00     /* Transmit Channel 13 */
-#define                 MUTE_CH13  0x8000     /* Mute Channel 13 */
-#define                nMUTE_CH13  0x0
-#define                   TX_CH14  0x3f0000   /* Transmit Channel 14 */
-#define                 MUTE_CH14  0x800000   /* Mute Channel 14 */
-#define                nMUTE_CH14  0x0
-#define                   TX_CH15  0x3f000000 /* Transmit Channel 15 */
-#define                 MUTE_CH15  0x80000000 /* Mute Channel 15 */
-#define                nMUTE_CH15  0x0
-
-/* Bit masks for MXVR_ROUTING_4 */
-
-#define                   TX_CH16  0x3f       /* Transmit Channel 16 */
-#define                 MUTE_CH16  0x80       /* Mute Channel 16 */
-#define                nMUTE_CH16  0x0
-#define                   TX_CH17  0x3f00     /* Transmit Channel 17 */
-#define                 MUTE_CH17  0x8000     /* Mute Channel 17 */
-#define                nMUTE_CH17  0x0
-#define                   TX_CH18  0x3f0000   /* Transmit Channel 18 */
-#define                 MUTE_CH18  0x800000   /* Mute Channel 18 */
-#define                nMUTE_CH18  0x0
-#define                   TX_CH19  0x3f000000 /* Transmit Channel 19 */
-#define                 MUTE_CH19  0x80000000 /* Mute Channel 19 */
-#define                nMUTE_CH19  0x0
-
-/* Bit masks for MXVR_ROUTING_5 */
-
-#define                   TX_CH20  0x3f       /* Transmit Channel 20 */
-#define                 MUTE_CH20  0x80       /* Mute Channel 20 */
-#define                nMUTE_CH20  0x0
-#define                   TX_CH21  0x3f00     /* Transmit Channel 21 */
-#define                 MUTE_CH21  0x8000     /* Mute Channel 21 */
-#define                nMUTE_CH21  0x0
-#define                   TX_CH22  0x3f0000   /* Transmit Channel 22 */
-#define                 MUTE_CH22  0x800000   /* Mute Channel 22 */
-#define                nMUTE_CH22  0x0
-#define                   TX_CH23  0x3f000000 /* Transmit Channel 23 */
-#define                 MUTE_CH23  0x80000000 /* Mute Channel 23 */
-#define                nMUTE_CH23  0x0
-
-/* Bit masks for MXVR_ROUTING_6 */
-
-#define                   TX_CH24  0x3f       /* Transmit Channel 24 */
-#define                 MUTE_CH24  0x80       /* Mute Channel 24 */
-#define                nMUTE_CH24  0x0
-#define                   TX_CH25  0x3f00     /* Transmit Channel 25 */
-#define                 MUTE_CH25  0x8000     /* Mute Channel 25 */
-#define                nMUTE_CH25  0x0
-#define                   TX_CH26  0x3f0000   /* Transmit Channel 26 */
-#define                 MUTE_CH26  0x800000   /* Mute Channel 26 */
-#define                nMUTE_CH26  0x0
-#define                   TX_CH27  0x3f000000 /* Transmit Channel 27 */
-#define                 MUTE_CH27  0x80000000 /* Mute Channel 27 */
-#define                nMUTE_CH27  0x0
-
-/* Bit masks for MXVR_ROUTING_7 */
-
-#define                   TX_CH28  0x3f       /* Transmit Channel 28 */
-#define                 MUTE_CH28  0x80       /* Mute Channel 28 */
-#define                nMUTE_CH28  0x0
-#define                   TX_CH29  0x3f00     /* Transmit Channel 29 */
-#define                 MUTE_CH29  0x8000     /* Mute Channel 29 */
-#define                nMUTE_CH29  0x0
-#define                   TX_CH30  0x3f0000   /* Transmit Channel 30 */
-#define                 MUTE_CH30  0x800000   /* Mute Channel 30 */
-#define                nMUTE_CH30  0x0
-#define                   TX_CH31  0x3f000000 /* Transmit Channel 31 */
-#define                 MUTE_CH31  0x80000000 /* Mute Channel 31 */
-#define                nMUTE_CH31  0x0
-
-/* Bit masks for MXVR_ROUTING_8 */
-
-#define                   TX_CH32  0x3f       /* Transmit Channel 32 */
-#define                 MUTE_CH32  0x80       /* Mute Channel 32 */
-#define                nMUTE_CH32  0x0
-#define                   TX_CH33  0x3f00     /* Transmit Channel 33 */
-#define                 MUTE_CH33  0x8000     /* Mute Channel 33 */
-#define                nMUTE_CH33  0x0
-#define                   TX_CH34  0x3f0000   /* Transmit Channel 34 */
-#define                 MUTE_CH34  0x800000   /* Mute Channel 34 */
-#define                nMUTE_CH34  0x0
-#define                   TX_CH35  0x3f000000 /* Transmit Channel 35 */
-#define                 MUTE_CH35  0x80000000 /* Mute Channel 35 */
-#define                nMUTE_CH35  0x0
-
-/* Bit masks for MXVR_ROUTING_9 */
-
-#define                   TX_CH36  0x3f       /* Transmit Channel 36 */
-#define                 MUTE_CH36  0x80       /* Mute Channel 36 */
-#define                nMUTE_CH36  0x0
-#define                   TX_CH37  0x3f00     /* Transmit Channel 37 */
-#define                 MUTE_CH37  0x8000     /* Mute Channel 37 */
-#define                nMUTE_CH37  0x0
-#define                   TX_CH38  0x3f0000   /* Transmit Channel 38 */
-#define                 MUTE_CH38  0x800000   /* Mute Channel 38 */
-#define                nMUTE_CH38  0x0
-#define                   TX_CH39  0x3f000000 /* Transmit Channel 39 */
-#define                 MUTE_CH39  0x80000000 /* Mute Channel 39 */
-#define                nMUTE_CH39  0x0
-
-/* Bit masks for MXVR_ROUTING_10 */
-
-#define                   TX_CH40  0x3f       /* Transmit Channel 40 */
-#define                 MUTE_CH40  0x80       /* Mute Channel 40 */
-#define                nMUTE_CH40  0x0
-#define                   TX_CH41  0x3f00     /* Transmit Channel 41 */
-#define                 MUTE_CH41  0x8000     /* Mute Channel 41 */
-#define                nMUTE_CH41  0x0
-#define                   TX_CH42  0x3f0000   /* Transmit Channel 42 */
-#define                 MUTE_CH42  0x800000   /* Mute Channel 42 */
-#define                nMUTE_CH42  0x0
-#define                   TX_CH43  0x3f000000 /* Transmit Channel 43 */
-#define                 MUTE_CH43  0x80000000 /* Mute Channel 43 */
-#define                nMUTE_CH43  0x0
-
-/* Bit masks for MXVR_ROUTING_11 */
-
-#define                   TX_CH44  0x3f       /* Transmit Channel 44 */
-#define                 MUTE_CH44  0x80       /* Mute Channel 44 */
-#define                nMUTE_CH44  0x0
-#define                   TX_CH45  0x3f00     /* Transmit Channel 45 */
-#define                 MUTE_CH45  0x8000     /* Mute Channel 45 */
-#define                nMUTE_CH45  0x0
-#define                   TX_CH46  0x3f0000   /* Transmit Channel 46 */
-#define                 MUTE_CH46  0x800000   /* Mute Channel 46 */
-#define                nMUTE_CH46  0x0
-#define                   TX_CH47  0x3f000000 /* Transmit Channel 47 */
-#define                 MUTE_CH47  0x80000000 /* Mute Channel 47 */
-#define                nMUTE_CH47  0x0
-
-/* Bit masks for MXVR_ROUTING_12 */
-
-#define                   TX_CH48  0x3f       /* Transmit Channel 48 */
-#define                 MUTE_CH48  0x80       /* Mute Channel 48 */
-#define                nMUTE_CH48  0x0
-#define                   TX_CH49  0x3f00     /* Transmit Channel 49 */
-#define                 MUTE_CH49  0x8000     /* Mute Channel 49 */
-#define                nMUTE_CH49  0x0
-#define                   TX_CH50  0x3f0000   /* Transmit Channel 50 */
-#define                 MUTE_CH50  0x800000   /* Mute Channel 50 */
-#define                nMUTE_CH50  0x0
-#define                   TX_CH51  0x3f000000 /* Transmit Channel 51 */
-#define                 MUTE_CH51  0x80000000 /* Mute Channel 51 */
-#define                nMUTE_CH51  0x0
-
-/* Bit masks for MXVR_ROUTING_13 */
-
-#define                   TX_CH52  0x3f       /* Transmit Channel 52 */
-#define                 MUTE_CH52  0x80       /* Mute Channel 52 */
-#define                nMUTE_CH52  0x0
-#define                   TX_CH53  0x3f00     /* Transmit Channel 53 */
-#define                 MUTE_CH53  0x8000     /* Mute Channel 53 */
-#define                nMUTE_CH53  0x0
-#define                   TX_CH54  0x3f0000   /* Transmit Channel 54 */
-#define                 MUTE_CH54  0x800000   /* Mute Channel 54 */
-#define                nMUTE_CH54  0x0
-#define                   TX_CH55  0x3f000000 /* Transmit Channel 55 */
-#define                 MUTE_CH55  0x80000000 /* Mute Channel 55 */
-#define                nMUTE_CH55  0x0
-
-/* Bit masks for MXVR_ROUTING_14 */
-
-#define                   TX_CH56  0x3f       /* Transmit Channel 56 */
-#define                 MUTE_CH56  0x80       /* Mute Channel 56 */
-#define                nMUTE_CH56  0x0
-#define                   TX_CH57  0x3f00     /* Transmit Channel 57 */
-#define                 MUTE_CH57  0x8000     /* Mute Channel 57 */
-#define                nMUTE_CH57  0x0
-#define                   TX_CH58  0x3f0000   /* Transmit Channel 58 */
-#define                 MUTE_CH58  0x800000   /* Mute Channel 58 */
-#define                nMUTE_CH58  0x0
-#define                   TX_CH59  0x3f000000 /* Transmit Channel 59 */
-#define                 MUTE_CH59  0x80000000 /* Mute Channel 59 */
-#define                nMUTE_CH59  0x0
-
-/* Bit masks for MXVR_BLOCK_CNT */
-
-#define                      BCNT  0xffff     /* Block Count */
-
-/* Bit masks for MXVR_CLK_CTL */
-
-#define                  MXTALCEN  0x1        /* MXVR Crystal Oscillator Clock Enable */
-#define                 nMXTALCEN  0x0
-#define                  MXTALFEN  0x2        /* MXVR Crystal Oscillator Feedback Enable */
-#define                 nMXTALFEN  0x0
-#define                  MXTALMUL  0x30       /* MXVR Crystal Multiplier */
-#define                  CLKX3SEL  0x80       /* Clock Generation Source Select */
-#define                 nCLKX3SEL  0x0
-#define                   MMCLKEN  0x100      /* Master Clock Enable */
-#define                  nMMCLKEN  0x0
-#define                  MMCLKMUL  0x1e00     /* Master Clock Multiplication Factor */
-#define                   PLLSMPS  0xe000     /* MXVR PLL State Machine Prescaler */
-#define                   MBCLKEN  0x10000    /* Bit Clock Enable */
-#define                  nMBCLKEN  0x0
-#define                  MBCLKDIV  0x1e0000   /* Bit Clock Divide Factor */
-#define                     INVRX  0x800000   /* Invert Receive Data */
-#define                    nINVRX  0x0
-#define                     MFSEN  0x1000000  /* Frame Sync Enable */
-#define                    nMFSEN  0x0
-#define                    MFSDIV  0x1e000000 /* Frame Sync Divide Factor */
-#define                    MFSSEL  0x60000000 /* Frame Sync Select */
-#define                   MFSSYNC  0x80000000 /* Frame Sync Synchronization Select */
-#define                  nMFSSYNC  0x0
-
-/* Bit masks for MXVR_CDRPLL_CTL */
-
-#define                   CDRSMEN  0x1        /* MXVR CDRPLL State Machine Enable */
-#define                  nCDRSMEN  0x0
-#define                   CDRRSTB  0x2        /* MXVR CDRPLL Reset */
-#define                  nCDRRSTB  0x0
-#define                   CDRSVCO  0x4        /* MXVR CDRPLL Start VCO */
-#define                  nCDRSVCO  0x0
-#define                   CDRMODE  0x8        /* MXVR CDRPLL CDR Mode Select */
-#define                  nCDRMODE  0x0
-#define                   CDRSCNT  0x3f0      /* MXVR CDRPLL Start Counter */
-#define                   CDRLCNT  0xfc00     /* MXVR CDRPLL Lock Counter */
-#define                 CDRSHPSEL  0x3f0000   /* MXVR CDRPLL Shaper Select */
-#define                  CDRSHPEN  0x800000   /* MXVR CDRPLL Shaper Enable */
-#define                 nCDRSHPEN  0x0
-#define                  CDRCPSEL  0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_FMPLL_CTL */
-
-#define                    FMSMEN  0x1        /* MXVR FMPLL State Machine Enable */
-#define                   nFMSMEN  0x0
-#define                    FMRSTB  0x2        /* MXVR FMPLL Reset */
-#define                   nFMRSTB  0x0
-#define                    FMSVCO  0x4        /* MXVR FMPLL Start VCO */
-#define                   nFMSVCO  0x0
-#define                    FMSCNT  0x3f0      /* MXVR FMPLL Start Counter */
-#define                    FMLCNT  0xfc00     /* MXVR FMPLL Lock Counter */
-#define                   FMCPSEL  0xff000000 /* MXVR FMPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_PIN_CTL */
-
-#define                  MTXONBOD  0x1        /* MTXONB Open Drain Select */
-#define                 nMTXONBOD  0x0
-#define                   MTXONBG  0x2        /* MTXONB Gates MTX Select */
-#define                  nMTXONBG  0x0
-#define                     MFSOE  0x10       /* MFS Output Enable */
-#define                    nMFSOE  0x0
-#define                  MFSGPSEL  0x20       /* MFS General Purpose Output Select */
-#define                 nMFSGPSEL  0x0
-#define                  MFSGPDAT  0x40       /* MFS General Purpose Output Data */
-#define                 nMFSGPDAT  0x0
-
-/* Bit masks for MXVR_SCLK_CNT */
-
-#define                      SCNT  0xffff     /* System Clock Count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define             nKPAD_IRQMODE  0x0        /* Interrupt Disabled */
-#define           KPAD_IRQMODE_SK  0x2        /* Single key (single row, single column) press interrupt enable */
-#define           KPAD_IRQMODE_MK  0x4        /* Single key press multiple key press interrupt enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3F)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
-
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFF)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
-
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0
-#define               KPAD_NO_KEY  0x0        /* No Keypress Status*/
-#define           KPAD_SINGLE_KEY  0x2        /* Single Keypress Status */
-#define            KPAD_MKSROWCOL  0x4        /* Multiple Keypress in the same row or column Status */
-#define            KPAD_MKMROWCOL  0x6        /* Multiple Keypress in the same multiple rows and multiple columns Status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0
-#define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0
-#define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* ************************ */
-/*   MXVR Address Offsets   */
-/* ************************ */
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-/* **************** */
-/*   MXVR Macros    */
-/* **************** */
-
-/* MXVR_CONFIG Macros */
-
-#define SET_MSB(x)       ( ( (x) & 0xF  ) << 9)
-
-/* MXVR_INT_STAT_1 Macros */
-
-#define DONEX(x)         (0x00000002 << (4 * (x)))
-#define HDONEX(x)        (0x00000001 << (4 * (x)))
-
-/* MXVR_INT_EN_1 Macros */
-
-#define DONEENX(x)       (0x00000002 << (4 * (x)))
-#define HDONEENX(x)      (0x00000001 << (4 * (x)))
-
-/* MXVR_CDRPLL_CTL Macros */
-
-#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
-
-/* MXVR_FMPLL_CTL Macros */
-
-#define SET_CDRCPSEL(x)  ( ( (x) & 0xFF ) << 24)
-#define SET_FMCPSEL(x)   ( ( (x) & 0xFF ) << 24)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF549_H */
author	cvs2svn <>	2008-11-19 18:25:20 +0000
committer	cvs2svn <>	2008-11-19 18:25:20 +0000
commit	ee40f8d491c436074cc576643f9d988b67319e8a (patch)
tree	2497a7463a68744ea4f715f0ac57f7798813d92d /libgloss/bfin/include/defBF549.h
parent	7562a08bb4d038699468d4c592a9f856f8e36c48 (diff)
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