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| author | Kaz Kylheku <kaz@kylheku.com> | 2018-04-18 20:25:22 -0700 |
|---|---|---|
| committer | Kaz Kylheku <kaz@kylheku.com> | 2018-04-18 20:25:22 -0700 |
| commit | d52dd126b35bfa0f6139a2dd4fb547493ed447bd (patch) | |
| tree | 578c89a26b52910d876501d77959744a016a1c66 | |
| parent | cec66e0bf8148d846efe16c31b74041eea3bb16d (diff) | |
| download | txr-d52dd126b35bfa0f6139a2dd4fb547493ed447bd.tar.gz txr-d52dd126b35bfa0f6139a2dd4fb547493ed447bd.tar.bz2 txr-d52dd126b35bfa0f6139a2dd4fb547493ed447bd.zip | |
asm: disassembler v-reg regression.
* share/txr/stdlib/asm.tl (operand-to-sym): To form v
registers, we must subtract 2 from the level, not add.
(operand-to-exp): Bug was propagated to this new
function, too.
| -rw-r--r-- | share/txr/stdlib/asm.tl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/share/txr/stdlib/asm.tl b/share/txr/stdlib/asm.tl index ed7ae1a0..edf0b67a 100644 --- a/share/txr/stdlib/asm.tl +++ b/share/txr/stdlib/asm.tl @@ -283,7 +283,7 @@ nil (intern (fmt "t~,02X" ix)))) (1 (intern (fmt "d~,02X" ix))) - (t (intern (fmt "v~,02X~,03X" (ssucc lv) ix)))))) + (t (intern (fmt "v~,02X~,03X" (ppred lv) ix)))))) (defun operand-to-exp (val) (with-lev-idx (lv ix) val @@ -292,7 +292,7 @@ nil ^(t ,ix))) (1 ^(d ,ix)) - (t ^(v ,lv ,ix))))) + (t ^(v ,(ppred lv) ,ix))))) (defun bits-to-obj (bits width) (let ((tag (logtrunc bits 2)) |