Add support for 64-bit ARM architecture: aarch64

7 files changed, 94 insertions, 73 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 3f16e042d..fc3469e6e 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,18 @@
+2012-08-16  Ian Bolton  <ian.bolton@arm.com>
+            Laurent Desnogues  <laurent.desnogues@arm.com>
+            Jim MacArthur  <jim.macarthur@arm.com>
+            Marcus Shawcroft  <marcus.shawcroft@arm.com>
+            Nigel Stephens  <nigel.stephens@arm.com>
+            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+            Richard Earnshaw  <rearnsha@arm.com>
+            Sofiane Naci  <sofiane.naci@arm.com>
+            Tejas Belagod  <tejas.belagod@arm.com>
+            Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* dis-asm.h (print_insn_aarch64): New declaration.
+	(print_aarch64_disassembler_options): New declaration.
+	(aarch64_symbol_is_valid): New declaration.
+
 2012-07-24  Stephan McCamant  <smcc@cs.berkeley.edu>
             Dr David Alan Gilbert  <dave@treblig.org>
 
diff --git a/include/dis-asm.h b/include/dis-asm.h
index 661e7cf58..25d44fcc3 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -220,6 +220,7 @@ typedef struct disassemble_info
    target address.  Return number of octets processed.  */
 typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
 
+extern int print_insn_aarch64		(bfd_vma, disassemble_info *);
 extern int print_insn_alpha		(bfd_vma, disassemble_info *);
 extern int print_insn_avr		(bfd_vma, disassemble_info *);
 extern int print_insn_bfin		(bfd_vma, disassemble_info *);
@@ -307,6 +308,7 @@ extern int print_insn_rl78		(bfd_vma, disassemble_info *);
 extern disassembler_ftype arc_get_disassembler (void *);
 extern disassembler_ftype cris_get_disassembler (bfd *);
 
+extern void print_aarch64_disassembler_options (FILE *);
 extern void print_i386_disassembler_options (FILE *);
 extern void print_mips_disassembler_options (FILE *);
 extern void print_ppc_disassembler_options (FILE *);
@@ -316,6 +318,7 @@ extern void print_s390_disassembler_options (FILE *);
 extern int  get_arm_regname_num_options (void);
 extern int  set_arm_regname_option (int);
 extern int  get_arm_regnames (int, const char **, const char **, const char *const **);
+extern bfd_boolean aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern void disassemble_init_powerpc (struct disassemble_info *);
 
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index ef84aa36a..eead26f7a 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,18 @@
+2012-08-16  Ian Bolton  <ian.bolton@arm.com>
+            Laurent Desnogues  <laurent.desnogues@arm.com>
+            Jim MacArthur  <jim.macarthur@arm.com>
+            Marcus Shawcroft  <marcus.shawcroft@arm.com>
+            Nigel Stephens  <nigel.stephens@arm.com>
+            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+            Richard Earnshaw  <rearnsha@arm.com>
+            Sofiane Naci  <sofiane.naci@arm.com>
+            Tejas Belagod  <tejas.belagod@arm.com>
+            Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h: New file.
+	* common.h (EM_res183): Rename to EM_AARCH64.
+	(EM_res184): Rename to EM_ARM184.
+
 2012-06-28  Iain Sandoe  <iain@codesourcery.com>
 
 	* common.h (AT_L1I_CACHESHAPE, AT_L1D_CACHESHAPE,
diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h
index 7787c681a..04730b17e 100644
--- a/include/elf/aarch64.h
+++ b/include/elf/aarch64.h
@@ -40,14 +40,14 @@
 
 START_RELOC_NUMBERS (elf_aarch64_reloc_type)
 
-/* Null relocations.  */
+/* Null relocations. */
 RELOC_NUMBER (R_AARCH64_NONE, 0) /* No reloc */
 
 FAKE_RELOC (R_AARCH64_static_min, 256)
 
 RELOC_NUMBER (R_AARCH64_NULL, 256) /* No reloc */
 
-/* Basic data relocations.  */
+/* Basic data relocations. */
 
 /* .xword: (S+A) */
 RELOC_NUMBER (R_AARCH64_ABS64, 257)
@@ -68,7 +68,7 @@ RELOC_NUMBER (R_AARCH64_PREL32, 261)
 RELOC_NUMBER (R_AARCH64_PREL16, 262)
 
 /* Group relocations to create a 16, 32, 48 or 64 bit
-   unsigned data or abs address inline.  */
+   unsigned data or abs address inline. */
 
 /* MOV[ZK]:   ((S+A) >>  0) & 0xffff */
 RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0,		263)
@@ -93,7 +93,7 @@ RELOC_NUMBER (R_AARCH64_MOVW_UABS_G3, 269)
 
 /* Group relocations to create high part of a 16, 32, 48 or 64 bit
    signed data or abs address inline. Will change instruction
-   to MOVN or MOVZ depending on sign of calculated value.  */
+   to MOVN or MOVZ depending on sign of calculated value. */
 
 /* MOV[ZN]:   ((S+A) >>  0) & 0xffff */
 RELOC_NUMBER (R_AARCH64_MOVW_SABS_G0, 270)
@@ -105,7 +105,7 @@ RELOC_NUMBER (R_AARCH64_MOVW_SABS_G1, 271)
 RELOC_NUMBER (R_AARCH64_MOVW_SABS_G2, 272)
 
 /* Relocations to generate 19, 21 and 33 bit PC-relative load/store
-   addresses: PG(x) is (x & ~0xfff).  */
+   addresses: PG(x) is (x & ~0xfff). */
 
 /* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
 RELOC_NUMBER (R_AARCH64_LD_PREL_LO19, 273)
@@ -125,20 +125,20 @@ RELOC_NUMBER (R_AARCH64_ADD_ABS_LO12_NC, 277)
 /* LD/ST8: (S+A) & 0xfff */
 RELOC_NUMBER (R_AARCH64_LDST8_ABS_LO12_NC, 278)
 
-/* Relocations for control-flow instructions.  */
+/* Relocations for control-flow instructions. */
 
-/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff.  */
+/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff */
 RELOC_NUMBER (R_AARCH64_TSTBR14, 279)
 
-/* B.cond: ((S+A-P) >> 2) & 0x7ffff.  */
+/* B.cond: ((S+A-P) >> 2) & 0x7ffff */
 RELOC_NUMBER (R_AARCH64_CONDBR19, 280)
 
 /* 281 unused */
 
-/* B:      ((S+A-P) >> 2) & 0x3ffffff.  */
+/* B:      ((S+A-P) >> 2) & 0x3ffffff */
 RELOC_NUMBER (R_AARCH64_JUMP26, 282)
 
-/* BL:     ((S+A-P) >> 2) & 0x3ffffff.  */
+/* BL:     ((S+A-P) >> 2) & 0x3ffffff */
 RELOC_NUMBER (R_AARCH64_CALL26, 283)
 
 /* LD/ST16: (S+A) & 0xffe */
diff --git a/include/elf/common.h b/include/elf/common.h
index 58e489afe..1c681d562 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -287,8 +287,8 @@
 #define EM_L1OM		180	/* Intel L1OM */
 #define EM_K1OM		181	/* Intel K1OM */
 #define EM_INTEL182	182	/* Reserved by Intel */
-#define EM_res183	183	/* Reserved by ARM */
-#define EM_res184	184	/* Reserved by ARM */
+#define EM_AARCH64	183	/* ARM 64-bit architecture */
+#define EM_ARM184	184	/* Reserved by ARM */
 #define EM_AVR32	185	/* Atmel Corporation 32-bit microprocessor family */
 #define EM_STM8	186	/* STMicroeletronics STM8 8-bit microcontroller */
 #define EM_TILE64	187	/* Tilera TILE64 multicore architecture family */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4b8d3002c..fad39303d 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,16 @@
+2012-08-16  Ian Bolton  <ian.bolton@arm.com>
+            Laurent Desnogues  <laurent.desnogues@arm.com>
+            Jim MacArthur  <jim.macarthur@arm.com>
+            Marcus Shawcroft  <marcus.shawcroft@arm.com>
+            Nigel Stephens  <nigel.stephens@arm.com>
+            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+            Richard Earnshaw  <rearnsha@arm.com>
+            Sofiane Naci  <sofiane.naci@arm.com>
+            Tejas Belagod  <tejas.belagod@arm.com>
+            Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h: New file.
+
 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h: Fix a typo in description.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 3a26199a1..f3db103ba 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -34,7 +34,7 @@ typedef uint32_t aarch64_insn;
 
 /* The following bitmasks control CPU features.  */
 #define AARCH64_FEATURE_V8	0x00000001	/* All processors.  */
-#define AARCH64_FEATURE_CRYPTO	0x00010000	/* Crypto instructions.  */
+#define AARCH64_FEATURE_CRYPTO	0x00010000	/* Crypto instructions. */
 #define AARCH64_FEATURE_FP	0x00020000	/* FP instructions.  */
 #define AARCH64_FEATURE_SIMD	0x00040000	/* SIMD instructions.  */
 
@@ -45,25 +45,21 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */
 
-/* CPU-specific features.  */
+/* CPU-specific features */
 typedef unsigned long aarch64_feature_set;
 
 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)	\
   (((CPU) & (FEAT)) != 0)
 
 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)	\
-  do						\
-    {						\
-      (TARG) = (F1) | (F2);			\
-    }						\
-  while (0)
+  do {						\
+    (TARG) = (F1) | (F2);			\
+  } while (0)
 
 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)	\
-  do						\
-    { 						\
-      (TARG) = (F1) &~ (F2);			\
-    }						\
-  while (0)
+  do {						\
+    (TARG) = (F1) &~ (F2);			\
+  } while (0)
 
 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 
@@ -600,7 +596,7 @@ opcode_has_special_coder (const aarch64_opcode *opcode)
 
 struct aarch64_name_value_pair
 {
-  const char *  name;
+  const char	*name;
   aarch64_insn	value;
 };
 
@@ -691,7 +687,7 @@ struct aarch64_opnd_info
 	  /* Lane index; valid only when has_index is 1.  */
 	  unsigned index : 4;
 	} reglist;
-      /* e.g. immediate or pc relative address offset.  */
+      /* e.g. immediate or pc relative address offset. */
       struct
 	{
 	  int64_t value;
@@ -851,75 +847,54 @@ typedef struct aarch64_operand_error aarch64_operand_error;
 
 /* Encoding entrypoint.  */
 
-extern int
-aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
-		       aarch64_insn *, aarch64_opnd_qualifier_t *,
-		       aarch64_operand_error *);
+int aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
+			   aarch64_insn *, aarch64_opnd_qualifier_t *,
+			   aarch64_operand_error *);
 
-extern const aarch64_opcode *
-aarch64_replace_opcode (struct aarch64_inst *,
-			const aarch64_opcode *);
+const aarch64_opcode* aarch64_replace_opcode (struct aarch64_inst *,
+					      const aarch64_opcode *);
 
 /* Given the opcode enumerator OP, return the pointer to the corresponding
    opcode entry.  */
 
-extern const aarch64_opcode *
-aarch64_get_opcode (enum aarch64_op);
+const aarch64_opcode* aarch64_get_opcode (enum aarch64_op);
 
 /* Generate the string representation of an operand.  */
-extern void
-aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
-		       const aarch64_opnd_info *, int, int *, bfd_vma *);
+void aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
+			    const aarch64_opnd_info *, int, int *, bfd_vma *);
 
 /* Miscellaneous interface.  */
 
-extern int
-aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
+int aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 
-extern aarch64_opnd_qualifier_t
+aarch64_opnd_qualifier_t
 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 				const aarch64_opnd_qualifier_t, int);
 
-extern int
-aarch64_num_of_operands (const aarch64_opcode *);
+int aarch64_num_of_operands (const aarch64_opcode *);
 
-extern int
-aarch64_stack_pointer_p (const aarch64_opnd_info *);
-
-extern
+int aarch64_stack_pointer_p (const aarch64_opnd_info *);
 int aarch64_zero_register_p (const aarch64_opnd_info *);
 
 /* Given an operand qualifier, return the expected data element size
    of a qualified operand.  */
-extern unsigned char
-aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
-
-extern enum aarch64_operand_class
-aarch64_get_operand_class (enum aarch64_opnd);
-
-extern const char *
-aarch64_get_operand_name (enum aarch64_opnd);
-
-extern const char *
-aarch64_get_operand_desc (enum aarch64_opnd);
+unsigned char aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
+enum aarch64_operand_class aarch64_get_operand_class (enum aarch64_opnd);
+const char* aarch64_get_operand_name (enum aarch64_opnd);
+const char* aarch64_get_operand_desc (enum aarch64_opnd);
 
 #ifdef DEBUG_AARCH64
 extern int debug_dump;
-
-extern void
-aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
-
-#define DEBUG_TRACE(M, ...)					\
-  {								\
-    if (debug_dump)						\
-      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
-  }
-
-#define DEBUG_TRACE_IF(C, M, ...)				\
-  {								\
-    if (debug_dump && (C))					\
-      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
-  }
+void aarch64_verbose (const char *str, ...)
+     __attribute__ ((format (printf, 1, 2)));
+#define DEBUG_TRACE(M, ...) {					\
+  if (debug_dump)						\
+    aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
+}
+#define DEBUG_TRACE_IF(C, M, ...) {				\
+  if (debug_dump && (C))					\
+    aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
+}
 #else  /* !DEBUG_AARCH64 */
 #define DEBUG_TRACE(M, ...) ;
 #define DEBUG_TRACE_IF(C, M, ...) ;